How to change the sampling rate.

[susuper]

I am using a compactrio 9074 chasis with 2 NI9234 and 2 Ni9236 module.

The problem bother me for 3 weeks is I can not change sampling rate.

I used FPGA wizard to generate FPGA vi and host Vi, then modify them by the suggestions from the tech support hotline. But still the maximum sampling rate is around 100Hz.

I need 1000-2000Hz sampling rate.

[Justin_P]

Hi Su,

I would suggest looking at the example project "Analog Input - cRIO.lvproj" and take a look at how the sampling rate is being handled in it.

[rex1030]

There are a few fundamental things wrong with your code. To start, look up the 9236 example and the 923x continuous acquisition example. You are using the correct structure of continuous acquisition except that you need to set the rate on the fpga like in the 9236 example.

Also, most importantly, you cannot read from both module types in the same fpga read loop if you are trying to continuously acquire data. This structure would be fine if you were requesting a finite data set on command, but you aren't. These two modules have completely different sample rate multipliers and clocks. You need two simultaneous read/write loops; one for each of the module types. In each read/write loop you are reading from all the channels of one module type and writing to a DMA FIFO channel. I usually use a different DMA channel for each type to simplify things but this may not be necessary for you.

I am attaching a modified version of the 9236 FPGA example that acquires from a 9236 and 9237 module continuously. Notice the separate loops and data rates. The 9236 acquires at 1 ks/s. The 9237 is recording at 10ks/s but is only writing to the fifo once every ten data points to match the amount of data per second as the 9236 acquire loop.

I hope by examining the examples I told you about you will understand what needs to happen for the 9236 to be able to acquire and then using my example can adapt for multiple module types. The key is really the 923x continuous example. 

I forgot to mention, be sure to set each module type's rate as a seperate fpga property. If you try to combine them, one of the rates will be coerced to default value, usually the fastest, and will result in more buffer overflow problems. 

Message Edited by rex1030 on 07-08-2009 03:43 PM