How to add DSP to FPGA in the 5170R "Stream To Host" project?

[Alexej_P]

I've borrowed the PXIe-5170R card with FPGA. So far I worked with multi-function DAQs (like 6361 and 6124) and the oscilloscope PXI-5922. Usually I work with continuous acquisition of 2-4 channels. Sampling rate, say, 1-5 Mss and I make one RMS or ARV value of each N measured points for each channel, one RMS point of 0.05-5 msec.

If I measure just one channel, the program is able to 1) band-pass the signal (N points); 2) Calculate RMS for each N points. For two channels or more the program is not fast enough.

So, using FPGA of 5170R for DSP like band-bass and RMS calculation (or evaluation Lock-in signal after multiplying by Sin(wt) and Cos(wt) the signal and summing) could be a very attractive way for high-speed acquisition.

I could not find manuals/tutorials (PDF?) for using FPGA on high-speed oscilloscopes, only simple tasks on point-by-point acquisition. By the way, the page with offline NI help viewer is broken

http://www.ni.com/en-us/support/downloads/package-help-viewer.56.html

I created a project from the template "Stream To Host (NI PXIe-5170R/5171R)". It loaded for 5 minutes and looks complicated inside. There can I find a tutorial how somebody created this project? The context help for subVIs here does not show "detailed help" like for all built-in LabView subvis. Where did these subVIs came from?

So, I need, say, 4 Chans at 5 Mss, read every N points (say 5000) band-pass them (say 1..50 kHz), calculate RMS. Do I need to insert

1) Down-sampling VI from 250 to 5 Mss. It is better than decimation, is not it? (Or should I skip this step?)

2) Band-pass each N points at  5 Mss for each channel resulting in 5/N Mss signal rate.

3) Calculate RMS value from N band-passed points for each channel.

Where can I put all these VIs, before the first pink feedback node?

These subVIs go one after another, but the timed loop has somehow to make all calculations in parallel. Will it be able to do it?

The compilation time 30-60 minutes after each FPGA.vi modification frightens me. Can I test all these techniques in the simulation mode? What parameters should I change in the program?