How to access the emulation of an FPGA from a driver? (and more emulation questions)

[Creation]

Hi

I have questions about the emulation feature of LabVIEW FPGA.

First of all. I already have a code for FPGA running on an real NI FPGA. But all the processing is done through a driver written in other language with an interface in LabVIEW. The interface has functions like download the bitfile to the FPGA, close, reset, access to the registers and so on. This has access to the FPGA not through the VI that generated the bitfile, but directly to the FPGA using the interface.

1. When running a vi in emulation mode is it possible to access the FPGA (the fake FPGA) from the driver using this interface? (a virtual FPGA is created that can be accessed?)

2. How do I generate real inputs for the emulation? Can I create a VI that gives this inputs?

3. How realistic are the results when using an emulator? Can this be considered as a good simulation of how everything will work on a real FPGA?

Thank you

[AdnanZ]

1. It depends on how you are running your application. The way I understand this, you run your host VI which corresponds with the FPGA to get data which you then process using code written in another programming language. And, you correspond with the FPGA by downloading and running a bitfile. Am I right? If that's the case, then I believe you cannot simulate the FPGA when you are using the bitfile. You will need to use the FPGA VI if you want to emulate and correspond with it using the Project Explorer Window. At that point, you will need to configure the Open FPGA VI Reference in the host VI to correspond with the FPGA VI and change the debugging option on the FPGA target properties to use simulation.

2. Yes, you can do either but it depends on what sort of hardware you are using. For both cases, right-click an FPGA target in the Project Explorer window and select Properties from the shortcut menu to display the FPGA Target Properties dialog box and select debugging from the category list. You can choose Execute VI on Development Computer with Simulated I/O option to specify whether to Use Random Data for FPGA I/O Read or Use Custom VI for FPGA I/O when executing the FPGA VI on a development computer. If you want to use a custom VI, you can start from a template. Refer to the tutorial, Creating Test Benches topic in the LabVIEW Help for more information about using that template.

Or you can choose the Execute VI on Development Computer with Real I/O to execute the FPGA VI on the development computer using I/O from the FPGA target. Remember, some FPGA targets do not support this option and some FPGA targets that support this option do not support all I/O resources. Not sure what those FPGA targets are.

3. Since this code is not running completely on the FPGA target yet, it will not reflect the program's speed or jitter performance. But, I find it good enough to test if my FPGA application and host application are communicating correctly and if I have programmed the application properly.