How many encoders interface with RIO 7811R

[servo]

I need 40 incremental encoder inputs for my motion application in PXI. I just need 16 bit up/down counter for the encoder. NI has 8 channel 32 bit up/down counter board PXI-6602, so I need 5 that boards. I am considering the use of Reconfigurable Digital I/O Using the LabVIEW FPGA Module PXI-7811R.

I would like to know how many encoder counters (16-bit) I can put in the PXI-7811R.

Thank you for your advice in advance.

Jae Woong

[Christian_L]

Jae,

The number of encoders you will be able to fit on the FPGA depends on the complexity of the code you will be using for the encoder input. I did a basic test with the default quadrature encoder input example shipped with LabVIEW FPGA 7.1 to implement 10 encoder inputs. This used up 13% of the FPGA. SoI feel condfident that you will be able to implement 40 encoders.

I have included the 10 encoder example.

Christian L
NI Consulting Services

[servo]

Thank you.

I want to use RIO PXI-7811R in PXI platform with PXI controller 8184 RT. I would like to know how the 8184RT can get data from RIO PXI-7811R? Through PXI bus or other communication path? In 8184 RT, I will run LabVIEW Real-Time.

Thank you in advance.

Jae Woong

[Arun_V]

Hello Jae,

The PXI FPGA board uses the PCI bus in the backplane of the PXI chassis to communicate to the RT Controller.

Regards,

Arun V
National Instruments

[Christian_L]

The hardware interface is the PCI bus which is part of the PXI backplane. In LabVIEW RT you will be using the LV FPGA host interface functions. These are installed as part of the NI-RIO driver. These functions abstract the hardware interface and provide an easy-to-use programming interface for downloading the VI to the FPGA and accessing the front panel controls of the FPGA VI.

Using the front panel of the FPGA VI you can implement different data transfer mechanisms. One indicator on the front panel will be used to expose the data from the FPGA VI so that you can read it from the RT application. If you need a synchronized or lossless data transfer you will use additional controls and indicators (Booleans) to 'handshake' data from the FPGA to the host.