The hardware interface is the PCI bus which is part of the PXI backplane. In LabVIEW RT you will be using the LV FPGA host interface functions. These are installed as part of the NI-RIO driver. These functions abstract the hardware interface and provide an easy-to-use programming interface for downloading the VI to the FPGA and accessing the front panel controls of the FPGA VI.
Using the front panel of the FPGA VI you can implement different data transfer mechanisms. One indicator on the front panel will be used to expose the data from the FPGA VI so that you can read it from the RT application. If you need a synchronized or lossless data transfer you will use additional controls and indicators (Booleans) to 'handshake' data from the FPGA to the host.
authored byChristian L, CLA
Systems Engineering Manager - Automotive and Transportation
NI - Austin, TX