How does one tell if an FPGA is in run mode

[sth]

This should be a standard feature but I can't find it in the help and I haven't seen a solution in the examples.  I am still fairly new on FPGA programming but this would seem to be something that is regularly done.

I have a cRIO system and the FPGA has some essential tasks.  The RT system will be to monitor and communicate with a less critical nature.  My question is if I want to restart the RT program without interrupting the execution of the FPGA which I would like to keep running.  This seems to work if one stops the RT system without stopping the FPGA.

Now on restarting the RT system, I open a FPGA reference to the bit file, and if the FPGA is not running, I want to start it.   If it is running I just want to start clearing and reading the FIFO.  How does one detect those two cases and deal with it?  None of the FPGA methods seems to give the status of the FPGA itself.  I can tell by looking at the physical hardware and seeing if the user LED is blinking but that is not really a programmatic solution. 🙂

[nathand]

The FPGA Run method is a no-op if the FPGA is already running, so you can safely Run your FPGA even if it's already running, so it seems like you could do the same thing regardless of whether or not the FPGA is already running. Does that work for you?

[sth]

Thanks, I was hoping that was true.  But I do want to initialize it differently setting parameters from a file if it isn't running.  If this is a fresh startup that is one thing, and if it is a running system I want to do a whole lot less and just connect to the FIFOs and send data to the network.

It appears that even the warning code back from the run command does not give an "already running" indication.  I am checking that further now.  Certainly the "open FPGA" reference does not seem to give a "FPGA running" warning.

[nathand]

Put a boolean indicator on the FPGA front panel and wire a false constant to it (outside any loop). You might be fine with just setting the default value to false, but I'm not sure all indicators reset to default values if you stop and restart an FPGA VI without resetting the FPGA. Check the value of that control after you Run the FPGA - if it's false, it's the first run. Then write a True value to it from the host. It's not perfect because your host code could presumably die between running the FPGA and setting the boolean, but it's unlikely.

I don't know of any approach that you can generalize to any unmodified FPGA code, but maybe someone else has one.

[sth]

Ok, I can build my own, this thing I am writing has so many interlocking watchdog timers that a signal can be arranged.  However it just seemed weird that the FPGA status was not available as a property.  The ability to stop and start the FPGA is certainly there, so the status is an actual property but just not available to the RT system.