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How do I know what is the host-side FIFO depth?

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Hi.

 

In LabVIEW FPGA, the FIFO.Configure Method lets you determine the depth of the FIFO on the <u>host</u> side.

 

If my VIs have never included this method, is there a way of knowing how deep this FIFO has been all along?

 

I set my FPGA-side FIFO to be 8k deep.  What depth does the host-side FIFO default to?

 

I am asking because I am getting some failures in my test VI that uses FIFOs and I suspect overflows are to blame.

 

Thanks,

 

AlejandroZ

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Here is a copy+paste from a post I made back in May 2010.  I'll add some tags to the original so it should facilitate easier searching.

 

The DMA FIFO is actually implemented in 2 parts, you define the FPGA size in the project explorer(actual FPGA fabric), the Host side is defined programatically (Host RAM).

 

There is a configure method you can run on the Host, the default for the Host side is 10,000 elements.  I would set the FPGA side much smaller, 1000 or so elements, save a lot of FPGA fabric.  Configure the Host side to 64,000 or something.

 

Here is a help link to the Configure method:

http://zone.ni.com/reference/en-XX/help/371599E-01/lvfpgahost/fpga_method_fifo_config/

 

and a link to the DMA FIFO help:

http://zone.ni.com/reference/en-XX/help/371599E-01/lvfpgaconcepts/pfi_data_transfer/#DMA_FIFOs

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Hi,

 

Thanks a lot for your response.  I had looked at the help for the Configure method and had seen that if left unwired it defaults to 10,000 elements.  However, I wonder if this also means that if the Configure method is never executed, the host-side FIFO size will also default to 10,000.

 

Are you sure this is the case?

 

Thanks,

 

AlejandroZ

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Accepted by topic author AlejandroZ

Yes it is still the default 10,000.  This can be checked with the FIFO.Write method and checking the number of empty elements remaining, although this requires the FIFO to be setup as Host to Target.

For a Target to Host it is assumed it defaults to 10,000 without calling the FIFO.Configure method, the only way I can think to test this is to make an FPGA VI loop writes to the FIFO and waits for a timeout, then check the iteration counter.  It can be checked by using the Configure method and reading the depth, however this does execute the method.

 

 

In short, I believe the default is 10,000, although I am not 100% sure for all cases.  I have verified 2 cases for my projects, using the Write method, and reading the depth using the configure method.

 

Is that a round about enough answer without committing? 🙂

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OK.  I'll take your word for it.  Thanks for your response.

 

AlejandroZ

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