How can I use LabView to control Altera Scripting

[Suppy]

I am getting error when I tried to load the .cdf file. It is showing passive mode is illegal. I have attached the error page. 

[JohnM67]

You forgot to load the pfl first, that acts as your boot strap and allows access to the flash.  I keep all the files in the bin folder, rember I had to moved the the pfl from there. The is a PFL for every FPGA types you you are going to have to search for it

quartus_pgm.exe  -c USB-BLASTER -m JTAG -o P;pfl_XXXXX.sof

Hit enter

Then type

quartus_pgm.exe  -c USB-BLASTER -m JTAG  test_2.cdf

you may or may not need the -m JTAG sytax, I don't have Altera installed any more so I can't look

I had this documented in my code.  

pfl output

Info: *******************************************************************
Info: Running Quartus II 32-bit Programmer
    Info: Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Full Version
    Info: Copyright (C) 1991-2012 Altera Corporation. All rights reserved.
    Info: Your use of Altera Corporation's design tools, logic functions
    Info: and other software and tools, and its AMPP partner logic
    Info: functions, and any output files from any of the foregoing
    Info: (including device programming or simulation files), and any
    Info: associated documentation or information are expressly subject
    Info: to the terms and conditions of the Altera Program License
    Info: Subscription Agreement, Altera MegaCore Function License
    Info: Agreement, or other applicable license agreement, including,
    Info: without limitation, that your use is for the sole purpose of
    Info: programming logic devices manufactured by Altera and sold by
    Info: Altera or its authorized distributors.  Please refer to the
    Info: applicable agreement for further details.
    Info: Processing started: Mon Oct 07 17:25:05 2013
Info: Command: quartus_pgm -c USB-BLASTER -m JTAG -o P;pfl_xxxxx.sof
Info (213045): Using programming cable "USB-Blaster [USB-0]"
Info (213011): Using programming file pfl_xxxxxxxx.sof with checksum 0x00317339 for device XXXXXXXX@1
Info (209060): Started Programmer operation at Mon Oct 07 17:25:07 2013
Info (209016): Configuring device index 1
Info (209017): Device 1 contains JTAG ID code 0xXXXXXXX
Info (209007): Configuration succeeded -- 1 device(s) configured
Info (209011): Successfully performed operation(s)
Info (209061): Ended Programmer operation at Mon Oct 07 17:25:13 2013
Info: Quartus II 32-bit Programmer was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 176 megabytes
    Info: Processing ended: Mon Oct 07 17:25:13 2013
    Info: Elapsed time: 00:00:08
    Info: Total CPU time (on all processors): 00:00:01

[akanaume]

thank you very much 

just want to ask if the communication between  Intel FPGA and LabVIEW can be bi-directional