Hi all, I'm currently using PCIe-7851r fpga card to drive my device. There were 64 lines to be controlled. So what I did is generating the commands on the host pc and then transfer it to the target via DMA FIFO. The data type of the FIFO is U64, i.e. every one digit controls 64 DIO lines. But the question becomes complex when I transfer 66 line command. I tried to create 2 FIFOs, but I can hardly make the 2 FIFOs synchronized.
I think I might be able to create 2 U64 arrays, one contains the original 64 line command,s and the other contains the 2 line info (a waste). And then I interleave them in the host and decimate them in the target. There should be enough cycles to to this. But I dont think this is a good solution. Is there any better method? Thank you.
LabVIEW 2009, Windows XP, PCIe-7851R
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