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Host to Target DMA transfer

Dear All,

I have been using DMA to transfer data from FPGA to host for along time. But I now want to transfer data from the host to FPGA. I however have problems doing so. What could be wrong with my problem?

I am reading data from a text tile and I want to transfer the data to FPGA and then read the values via an indicator from the host end. I however don't see any data passed to the indicator (Data X).

Any suggestions will be highly appreciated (I have attached my VIs and snapshots)

 

Thank you.

 

Kind regards,

Benvalet

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There are several things wrong here, if the goal is:

  • to transfer the data to FPGA and then read the values via an indicator from the host end

Look at your Host code; how many elements are written every 100 milliseconds?

  • I do not know what is in your text file and you do not configure the FIFO. Without configuration, according to the help, the FIFO size defaults to 10,000 or 16,384, depending on the version of NI-RIO. Let's pretend this code puts 16,384 elements in the the FIFO every 100 milliseconds.

Meanwhile in your FPGA code, how long does it take to read that many elements?

  • While there is data in the FIFO, it is being read at your FPGA clock speed. At 40 MHz, it would read all 16,384 elements in about 0.4 milliseconds, so even at 1 MHz it would only take 16 milliseconds.

Does this help explain what is going on? The FPGA reads the FIFO and writes X much faster than the Host could ever read an FPGA indicator.

I would expect that the Host code provide would show X as the last value in the text file, once the for loop completes.

With the FPGA code as written, if you really wanted to read back in the Host all the values written to the FIFO, you would need to create another FIFO that the FPGA writes to and the Host reads. You would also likely need two loops running in the Host.

Thanks for your time - Chris
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Dear Chris,

This was very helpful. I appreciate for taking your time to read and respond to my question. Thank you.

 

Kind Regards,

Benvalet

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Hi Benvalet,

 

I need to stream data via FIFO from the Host to RT (FPGA).  Will you post your final working code?

 

Thanks,

JJ

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To provide more detail as to what I'm trying to do for anyone who might have suggestions, it is as follows. In the Host vi, I would like to load a text file containing four columns of int16 values, say 200,000 elements each.  Next, I want to write these values to a FIFO to have the effect of streaming/transferring them to the FPGA/RT vi.  On the FPGA vi side at 600Hz, I would read the elements from the FIFO, place them into a four element array, separate them into bytes, and transmit them out my FPGA UART code.  The UART code already exists and works.  I'm just looking for help on the piece of reading from a data file and writing the FIFO on the host side and then reading out the elements on the FPGA side at 600Hz.  Thanks much for any help!

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