回复： High-speed, continuous, large number data acquisition with NI 7965R and 5761

[yhlpc]

Hardware :

     NI 7965R FlexRIO FPGA module 

     NI 5761 14 bit 250 MS/s digitizer

Software :

     LabVIEW 2011

     NI RIO - 4.1

     NI FlexRIO Adapter Module Support 3.4

     NI FlexRIO Instrument Development Library 1.1

First step, my Basic Aim is continuously,losslessly acquire periodic waveforms (1 KHz ~ 20 KHz) through 2 channels at 250 Ms/s for 1 sec, and clock is selectable.

Of course, some processing code could be added into the FPGA VI is much more better due to periodic waveforms.

So, my Final Aim is averaging many records (50 ~ 1000 records) of each periodic waveform for rejecting noise effect, and calculating spectrum of the average waveform with FFT. That's what I really want.

In order to achieve my goal, I almost found 2 methods.

1)  Using NI FlexRIO Instrument Development Library examples

          NI FlexRIO Development Tools authored by Ryan_V[DE] reduces users' programming difficulty and time. In this masterpiece, some examples are useful. I increased Host DMA FIFO Length to 8 000 000(almost maximum, otherwise error happens). and then executed the external clock example.The result showed that it can record 32 ms at 250 Ms/s, but it is still so short for my application.

          hope any genius give me some advice on increasing record time to 1 sec.

2)  Referencing similar case

          During searching technical post, How FPGA-Based Instruments Can Speed Up Measurements authored by The_Red_Barron and Architecting Streaming Applications with LabVIEW FPGA authored by aasenjo attracts me. the case is much similar with my final aim. I have done some work seeing atttached file (including project file and compile report),but I am a freshman to LabVIEW FPGA and I don't know how to test this project.

          hope to have this project test, send me some advice on final aim and also want the project file of this case study.

3) user-defined

          As Large number of samples through FIFO - avoid overflow on target buffer posted by ManuelQ, the FPGA vi is based on the lowest-level unit. So it is too diffcult for greenhand just like me.

This is what I recently found for my application.

hope talent to participate in discussion and any advice and discussion is appreciated.

Thanks in advance for any reply!

[yhlpc]

attached file

[Haagen-Dazs]

Hi yhlpc,

I was looking through the files you provided and the Flex RIO Development Library (FIDL) examples and I think you may be able to use one of our built in examples almost out of the box. In LabVIEW if you go to Help >> Find Examples there is an example in the directory Hardware Input and Output >> FlexRIO >> IO Modules >> NI 5761 >> NI 5761 Getting Started.lvproj. That example is configured for your module and FPGA target. In this example it can either acquire immediately or wait for a digital trigger. It is also configured to only acquire from one channel at a time but is a good starting point for your application. Notice how the loop uses the IO Module Clock which should get you the 250 MS/s clock on the 5761. Also notice the Samples Per Trigger control which is used to determine how many data points are acquired. To acquire 250 MS in one second then I believe we want the Samples Per Trigger to be set to 250 Million. Please let me know what you think of that example and if you have any follow up questions for me.

[yhlpc]

Hello Patrick，

       Thanks for your reply first!

       As your introduction, I inserted "Configuration" and "Start" invoke methods ouside the while loop in the HOST vi of NI 5761 Getting Started.lvproj.

       After my trial, I found that the maximum of HOST FIFO length is appro. 55M (far away from 250M). Although the HOST FIFO length could be set a large value, the accessible Samples Per Trigger is relatively small (maximum :~13M*0.5, namely 52 ms, better than FIDL method (32 ms) as previous).

       (FIFO data type is U32, computer RAM is 2 GB)

       I also wonder that the clocks in the NI 5761 Getting Started.lvproj are 40 MHz Onboard Clock, 200MHz Clock and IO Module Clock0(20 MHz), why it can take sample at 250 MS/s?

yhlpc

[Haagen-Dazs]

Hi Yhlpc,

I have been looking into what you had mentioned and the Module should be running at 250 MHz and if you look at the example you will notice that each read actually produces 2 samples. That is who we can use the IOModClock which runs at 125 MHz when passed through the FPGA. The second portion of your concern deals with the FIFO and I am curious how you are reading from the FIFO. I am nearly certain that your computer will not be able to read from the FIFO as fast as that example is writing to the FIFO. In that situation you need to ensure that you are reading larger chunks of data from the FIFO in order to keep up. You are able to increase the memory associated to the FIFO on the host or the size on the FPGA but I dont think you should need to do that for this application. Please let me know what you think and which 5761 connector you are using.

[yhlpc]

1. In the  NI 5761 Getting Started.lvproj, what is the purpose is using 200MHz Clock ? and IO Module Clock 0 is whether constant or defined by user ?  in this project, IO Module Clock0 is set to 20 MHz,is it correct?

2. in this project, FIFO length is 2047. My computer is NI PXIe-8133 and chassis is NI 1062Q, is it enough for achieving this application?

3. Although this project can record waveform at 250 MS/s for ~50 ms, it is also acceptable. Can you give me some advice on "2)  Referencing similar case" in the first message of this post?  the second message is my program and compile report.

[Dave.T]

1. The 200 MHz clock is used by the CLIP (VHDL) behind the scenes for proper data alignment.  It is required to compile the vi.  You do not need to do anything special with it beyond adding it to the project.  IO module clocking options are outlined on page 6 and 7 of the user manual. 

To adjust IO module clock from internal to external, see the NI 5761 - Clock Select.lvproj in the labview example finder.  

IO Module clock is not set to 20 MHz.  I'm not sure where you saw this, but I'm guessing it was in the right click -- properties menu of the IO Mod clock in the project.  This is not how the clock is set when using a FlexRIO. 

2. The FIFO length on the FPGA is set to 2047, there is another FIFO on the host computer that is set to a default of 20k elements (I believe).  Depending on how fast you're trying to send data, 2047 should be enough elements.  

The max throughput of a 7965R back to the host is under 800 MB/s.  If you exceed this, then the FIFO on the FPGA will begin to fill up. 

3. The similar cases you're referring to are a newsletter and a presentation on best practices for a multitude of streaming applications.  There is no specific project, as they are both meant to be general explainations of ways to approach different problems. 

In the end, you're going to have to have an understanding of LVFPGA high performance/high throughput programming.  We offer a High Throughput LabVIEW FPGA class several times a year in different locations. 

My advice is to start with the Getting Started example found in the example finder.  Provide it a known signal, make small adjustments to the FPGA vi until you get a better understanding of what's going on and how all the pieces are working together.  

Also, it sounds like what you're trying to do is to sample all your data on the FPGA, and stream it back to the host.  What do you plan on doing with it once it gets to the host?  

250 MSsamples/sec * 2 ch * 2 bytes/sample * 1 second = 1GB

As I mentioned earlier, the maximum throughput of the PXIe-7965R is under 800 MB/s.  This will vary from machine to machine (as a function of how fast your processor can read data from memory) You can more specifically benchmark this with the High Throughput Streaming.lvproj example found in the example finder.  

Since you're only interseted in 1 second's worth of data, I would probably approach the problem by buffering it using the onboard DRAM of the 7965R.  You've got 512 MB which can store the data temporarily while the DMA bus is transferring it all over. 

With DRAM, you can start by looking at the examples, and here is some more reading I would suggest: 

https://decibel.ni.com/content/message/4427#4427

http://forums.ni.com/t5/LabVIEW/DRAM-performance-on-flexrio-7965R/m-p/1331892?requireLogin=False

http://forums.ni.com/t5/LabVIEW/Labview-FPGA-DRAM-Address-question/m-p/1383624?requireLogin=False

[Haagen-Dazs]

1) In the getting started project the loop uses the IO Module Clock 0. This refers to the clock that is running on the adapter module which gets passed through the FPGA for use in that loop. That clock runs at a clock rate to achieve 250 MS/s and when that clock is passed to the FPGA it is divided down to 125 MHz. In that case we would be running 1/2 as fast as the adapter module can produce samples. To overcome this, the FPGA I/O node is returning 2 samples at a time. 

2) In that project there is some extra state machine information but the data from the FPGA I/O node is passed directly to a DMA FIFO. The DMA FIFO is divided into two segments, the FPGA side and the host computer side. In your case the FIFO on the FPGA is 2047 which means the FIFO on the host side is likely 10,000 elements. The DMA controller on the FPGA handles passing the data between the FPGA FIFO to the Host FIFO which essentially makes one big FIFO. The correct size is not easily determined but the question you need to ask yourself is if the Host side is reading the FIFO faster than the FPGA side is writing it. Most likely the host side will not be able to read fast enough so you will need to read a large number of samples during every read. In the example the host side is set to read 1000 elements per read and this may need to be bumped up to achieve the throughput you are looking for.

3) I am not sure I fully understand your question for number 3 but I believe that the FIDL is not the easiest and most direct way to complete this application. I did take a look at that code and it appears that you are writing a VI-Defined FIFO at 125 MHz and then reading it at 40 MHz which gets passed to an FFT and then passed to the host. This seems like a bottle neck for your application. Since you are only looking to grab 1 second of data you could pass the data to the memory of the FPGA and then pass it off later.