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High Through Put Example (LabView FPGA FlexRIO Memory)

High Through Put Example (LabView FPGA FlexRIO Memory)

‎05-18-2021 12:30 PM

I am trying to collect data from an ADC that samples at 2MHz, but the High Through Put Example in LabView FPGA FlexRIO runs at 125MHz and complains that I am not responding Quick enough at 63 Clock Cycles between ADC Sample rate.

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Re: High Through Put Example (LabView FPGA FlexRIO Memory)

‎05-19-2021 01:58 AM

Hi Edmund,

 

and what is the question?

 

Mind to attach your code, with some more detailed information on your problem(s)?

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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