Has anyone used 3-phase PLL for FPGA?

[Noriker]

3-phase Phase-Locked-Loop is an express VI for FPGA. I am testing it, but I cannot get right results. Could you point out what was wrong please?

I use "sine wave generator" to create 3 phase sine signal of 50Hz, and input to a 3-phase PLL. I hope to have 50Hz at it's output but the results are ranging from 25Hz to 75Hz.

Please note the enclosed vi only run on FPGA.

Many thanks for your help.

[LocalDSP · Accepted solution]

Your three Sine Wave Generators are configured to output 32 bit integers (I32) but the amplitude is set to 1, so your signals only have three possible levels (-1, 0, +1). It may not be the root cause of your problem but what happens if you change the amplitude to Full scale (check box on the configuration panel)?

You'll also have to revisit the Fixed-Point configuration on your PLL panel (for example input integer word length is set to 8 bit).

Btw. your VI works fine when tested on the host side, though it's slow. It may still be faster to test it on the host before re-compiling. Eventually re-scale your frequencies and loop timer value while debugging on the host to make it all converge faster.

[Noriker]

Hi, thanks very much for your help. It works and produces acurate result after tunning. Many thanks again.

[TheoLEDUC]

Hello, I work with LabVIEW & LabVIEW FPGA 2013.

I begin to work with PLL and I would have a look of your VI. Could you convert it to a LabVIEW 13 version ?

Thank you !