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Good practice to reduce I/O Node's FXP bit-width for FPGA Optimization?

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I'm reading from some cRIO cards that output <+/-,24,10> FXP's which is *much* wider than I need it to be.  I'm reading in voltages that are always positive and less than 100V and I have a 1mV accuracy requirement.


Is it good practice to immediately add a "To Fixed-Point" primitive after the I/O node to reduce a <+/-,24,10> to a <+,17,7> (in this case) to save 7 bits per I/O channel and possibly more if I do any sort of math upon them?



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Accepted by SeanDonner

Hi Sean,


when you are sure you don't need those extra bits then you can convert to a different FXP representation…

Best regards,

using LV2011SP1 + LV2017 (+LV2020 sometimes) on Win10+cRIO
Message 2 of 2