Frequency Shift to IQ Samples on FPGA

[ALST]

Good Morning to everyone,

I'm facing the following problem, and I really need some help.

I'm developing a VI on FPGA which has the following task: takes IQ samples as input from host through an Host to Tarhet FIFO. Then each sample as to be shift in frequency by a constant value (ex: 50KHZ) and then it has to be sent back to the Host using another FIFO.  Both the acquisition and generation parts works fine on my VI, but I'm not sure how to implement the signal processing one, that has to do the frequency shift, and I would love some suggest.

Thanks to everyone!

[Stefanorse02]

Hi 

Basically you need to implement a frequency shift on FPGA right? In which format are represented the IQ data? Which hardware are you using? 

[ALST]

Good evening,

my IQ data are represented as fixed point (word 18, Integer 1) and the hardware is a PXIe-7821R.

[Stefanorse02]

Hi

I think the best practice is to use the DSP Labview FPGA function: http://zone.ni.com/reference/en-XX/help/374500C-01/oscopes/idl_dsp_fpga/  (you find the frequency shift on the last part of the paper). Anyway if you want to do it manually you just need to multiply each IQ sample by the sin(50khz*2pi) is quite simple to do. Let me know 🙂

[ALST]

Hi,

the page you linked to me is not accessible, since it says "Page Error". However, are you sure about the formula? My calculation provides a result like sin(50khz*2pi*T), which is quite more diffuclt due to the presence of the time element. Maybe I'm wrong..

[Intaris]

I think the link is supposed to be THIS ONE,

[ALST]

Hi,

I tried to use the DSP, nut I'm not really sure about its working mode. In particular, I notice that when I put a frequency shift bigger than 0.2 I have a distorsion in the response. Moreover, I have a chirped input that is divide in two different parts, the first with increasing frequency and the second that is a decreasing frequency chirp. Applying the same shift, the first signal is increased while the second is deacreased, and this is not what I want to obtain.

[ALST]

One last question about the frequency shift block.

How can I determnine a-priori the data rate, if this is conditioned by the inpit acquisition rate, by the elaboration time of the blobk and by a series of other external condition?