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Flush DMA Target to Host FIFO FPGA

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I have a program running on FPGA that waits for a 1 ppr pulse from an encoder, then starts acquiring data based off 4096 ppr pulses. After it gets 4096 pulses, it syncs back up with the 1 ppr pulse and does it again. If the encoder stops rotating in the middle of a revolution, I have a timeout that will happen, should I not get a 4096 pulse in some alloted amount of time. This way my code doesn't get stuck waiting for pulses if the encoder stops spinning. Then, it notifies the user, and syncs back up with the 1 ppr pulse once the spinning resumes.


Well, let's say the encoder stops spinning half way through a revolution, I get a timeout, but now there are 2048 (4096 ppr * 0.5 revolutions) stale data points in the FIFO. I want to get rid of these points so that once it syncs back up with the 1 ppr pulse, I have data in the FIFO that's all from the current revolution. I suppose I could take the timeout error and trigger a loop on the RT side that dequeues elements until the FIFO is empty, but if this doesn't happen in time before the encoder starts spinning again, I could still get stuck with stale data. Maybe I need some sort of handshaking using controls? I could also put Target to Target FIFOs on the FPGA to store data and not queue it up to go to the host until it's all there. If I get a timeout, I could then flush the FIFOs on the FPGA, because there is a method available for flushing target to target FIFOs.


Anyone dealt with this problem before,and how did you resolve it?

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Accepted by GregFreeman



I think your first method is the best option. When you register a timeout, have it trigger a case on your RT side that first does a FIFO read that returns the number of elements in the FIFO (but reads zero elements) and then immediately do a FIFO read that reads the number of elements remaining. This will clear your FIFO and it should execute quickly.  

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