I am currently struggling to implement on-board
averaging using DRAM on our FlexRIO system (PXIe-1082, PXIe-8133,
PXIe-7965R, 5761R) - any help would be appreciated. I have LV 10 and did install the DRAM compliation bug fix found here.
What I want to accomplish
- Read in data from the 5761R at 100 MS/s with the 7965R (I16); use
either external or internal clock
- Sum consecutive frames of data samples on the 7965R using DRAM (a
frame is typically ~40'000 samples, but could go up to 1e6); max num
of summed frames should be large (use I32)
- After a pre-set number of summed frames, write the summed data
frame to DMA FIFO
- Start over
- Read summed data frame from DMA FIFO
- Save / process / display / ...
- Start over
There should be no deadtime (ie. no lost data points), but I don't
care about latency.
I also attached the current status of my (unsuccessful) attempt,
which compiles but generates invalid data (tested with a signal
This is be a better place to post NI FlexRIO questions as you can get better assistance through this resource.
Additionally, I noticed that you created an E-mail SR (7315913) today about the same issue, so one of our other Application Engineers will be contacting you directly very soon to address this issue. In fact, it may not be necessary to post on the FlexRIO community if you have already created an SR with us.