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FlexRIO DRAM for image frame transfer

Hi, 

 

We have FlexRIO PXIe-7972 with NI-1483 adapter module for camera-link interface (full), we are going to change image data-format into 10-Tap 16-bit and transfer to host PC. As show in the figure, I use "CamToTarge" DMA FIFO as a small buffer, and then transfer to the DRAM FIFO as a large frame buffer. One the target to host pc side, I utilize DRAM FIFO read and a packer transfer via "Host DMA U16" target to host DMA FIFO. I'm sure when is running, there are data from the camera. However, I cannot see any data output to host PC. The camera I used is 2060x2048 pixels with 16-bit data format. Any further information will be grateful, thanks. 

 

Best,

Yong

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Is anyone know how to transfer the whole frame image via DRAM FIFO on 797x series? The example code doesn't support for this version, thanks.

 

Best,

Yong 

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Hi,

 

I have not done image processing on FPGAs, but I can ask some general questions to help with trouble shooting.

 

You will only get data in your TargetToHost FIFO if the boolean chain controlling it goes True. Are you sure this will happen? Your boolean wires need to be better organised (and labelled) for me to understand which is ouput/input valid.

 

Your strategy is to read the camera data into a target-scoped FIFO. Process it. Output to a TargetToHost FIFO. Do you plan to transfer the enitre picture before you start processing or to start processing before you have the whole picture?

 

I guess the ACQ SM 2 subvi determines if the pixel integer inputs are valid on any given cycle. Why do you only read the 1st pixel of every 5 that arrive? Are you aware that target scoped FIFOs can use user defined structures? You don't need to convert to arrays, you can put the cluster straight in as the input.

 

I think the big challenge with your design is to ensure that the inputs are valid on any given cycle. I do not know much about the details on how the NI1483 can be used to achieve this, but your method seems sensible. Copying the help file is a good place to start.

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Hi, 

 

Thanks for reply and suggestions. The image data format of PCO.edge camera interface transfers 5 pixels at one time; therefore, I want to transfer 5 pixels with 16-bit data format via DRAM in single clock time loop (120 MHz). So far, I only successfully transfer one pixel per clock cycle via DRAM FIFO as figure "dramfifo 1pixel.png". The result is shown in figure "test2.png", only 1/5 frame is transfer, so sad. 

 

Best,

Yong

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Here is the figure "dramfifo2.png".

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Hi, MaxJoseph,

 

Thanks for suggestion. Definitely, I'm going to do process on FPGA in the future. So far, I just want to put frame into DRAM, and then transfer to host PC. The custom data type offered by NI example code only support 1 element. I still try to figure out how to transfer with 4 or 5 pixel with custom data type. The DMA FIFO can transfer 1, 2, 4 8, ... elements at single cycle loop, thanks. 

 

dramfifo2.png

 

Best,

Yong

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Sorry the above implants the wrong figure. Here is the latest update, thanks.

 

dramfifo 1pixel.png

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Ok, lets focus on making a target-scoped FIFO that is based on your own custom data type. To do this I create the FIFO in the project window and point it to a type def that I have made. This works well. You can use this to transfer the whole 5-pixel cluster straight to your Target To Host FIFO.

 

Then you will have to work out how to transfer your whole 5 pixels to your host. It sounds like you have an idea on how to do this.

 

I do not use the DRAM FIFO blocks when programming FGPAs, and instead use the invoke nodes on the FIFO references to put elements into FIFOs.

 

Why do you not just transfer the data straight into the Target To Host FIFO and avoid all the target scoped FIFO stuff?

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Hi, MaxJoseph,

 

Very thanks for your propose. Once it can transfer to host, I can write DLL(dynamic linked library) to rearrange the image pixel-by-pixel. To transfer into DRAM just because we are going to do some pre-process of image on FPGA, thanks.

 

Best,

Yong

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