Filter delay line in FPGA

[SunJab]

Hi,

How can I implement filter delay line using block RAM in labview FPGA?

thanks

[T-REX$]

Hi Sandee,

I think that this is usually done with a circular buffer, but depending on what you're doing, you could also use shift registers on a Single Cycle Time Loop. The implementation really depends on how many cycles you want to delay. If it's only a few, then I would go with the second method.

[SunJab]

I'm tryng to implement a higher order filter, for which, the number of delays (shift registers) will be equal to the numbers of filter taps. I have implemented the circular buffer for this using simple arrays. But i don't know how i'm going to do the same using block RAM on FPGA. I have read some where that the current FIFOs on FPGA donot support circular buffers. Is there any way i can use the block RAM to implement circular buffer...coz using the array of size equal to number of filter taps would be equivalent to using shift registers equal to number of filter taps.

thanks

[T-REX$]

Hi Sandee,

You will have to implement the logic for a circular buffer yourself, but you can use the FPGA Memory VIs to do it.

[SunJab]

Alright... Is there any limit on the maximum numbers of memory items that can be used in under one FPGA target as long as memory used by these memory items doesnot exceed the total avalable block RAM on FPGA ?? 

thanks

[T-REX$]

Hi Sandee,

There isn't any limit like that. As long as you don't go over, you should be just fine.

[srm@viewpointusa.com]

depending on the target there is a limit to the largest contiguous memory block that can be accessed.  It is typically large enough for applications and it will tell you when you configure the block how large it can be.