What I am simply trying to do is: acquire a single sample, do some processing, and then wait for the other sample. However, I asuume using the wait function would cause a very delegate situation in terms of timing. Pleas correct me if I am wrong in this assumption and suggest other ways if possible.
There is nothing wrong with adding a wait. The FPGA will be waiting for the next sample as soon as you try to do the read. I do not see any issues with timing just from your quick description.