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Hello everyone,

 

I am doing a project on myRIO-1900 (on the FPGA side). Its say's in the harware specification that the sampling rate is 500 Ksa/s, meaning that separation in time between consecutive samples is 2 us (assuming i am using only 1 channel). Now assume that we have an Analog input node inside an SCTL running at 40 MHz . My quesion is, if the SCTL finishes processing a single sample at 25 ns, what happens in the remaining period between the samples? Does labVIEW stay idle waiting for the next sample? or does it keep on reading the same value? If so, how is the SCTL by any means useful when acquiring an analog input from any application?

 

Thanks in advance,

Quick response is highly appreciated,

Hazem

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Message 1 of 11
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Loop with data reading will wait new data. So it will iterate 500 iteration in sec

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So it will keep reading the same value over and over until a new sample value is received ? If yes, then much more samples than expected will be processed and this will corrupt the functionality of the code. What is a possible solution for this? How can the acquisition be held until a new value is received?

 

Thanks a lot,

Hazem

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NO. I say loop will wait new data.
WILL WAIT.
You use 'get data' without "wait" and receive data as fast as possible (500 kHz in your case) but not faster.

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Sample data is not stored inside a queue. It is stored inside an array of memory. You only read the latest data. If you wait long enough, you will get fresh data.

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You have two threads named just "FPGA"

 

You really need to start using thread names that provide ANYTHING of value to people looking to help.  If they aren't the same question, you've named them poorly =/

 

SCTLs aren't typically useful when working with analog as you're bound by your ADC.  Most of the time, you'll get an error using analog here.  The FPGA will keep running at the clock rate you've given it.

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So let me rephrase what you are saying: No matter what the sampling rate is, the loop will seize to iterate and will wait "internally" until a new sample is received, Correct?

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Not sure who do you talk with. There is a separated circuit for ADC. It collects data and put in a buffer. If there is new data, it will be updated. What every you read is the content of that buffer.

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hazem93 wrote:  My quesion is, if the SCTL finishes processing a single sample at 25 ns, what happens in the remaining period between the samples? Does labVIEW stay idle waiting for the next sample? or does it keep on reading the same value? If so, how is the SCTL by any means useful when acquiring an analog input from any application?

Try to compile the FPGA.  You will get an error stating that the analog read takes more than 1 clock cycle and therefore cannot be in a SCTL.  So this whole question is actually quite mute.


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Message 9 of 11
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Thanks for reply. I am new to the forums so I find myself a little messy!

 

So I avoided SCTLs and tried to compile the I/O node inside a while loop. The compilation was successful. What I am simply trying to do is: acquire a single sample, do some processing, and then wait for the other sample. However, I asuume using the wait function would cause a very delegate situation in terms of timing. Pleas correct me if I am wrong in this assumption and suggest other ways if possible.

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