FPGA with digital I/O timing

[mittleiderj]

I have a FPGA vi running on a NI9074 target. The vi reads 32 digital inputs (NI9426)and based on the configuration of those 32 bits sets 24 digital outputs (NI9476). I have a loop timer within this same loop so I know how long it takes to run each iteration of the loop. What I don't quite understand is the timing of the digital outputs. I assume the digtal inputs are read within the same time frame as the loop (1200 ticks). My question is, is there a delay beyond the loop time before the digital outputs will register? I think the NI9476 has a 12ms update time(?) So will the actual loop time then be the loop time (1200 ticks) plus the update rate for the DO module (12ms)?

Thanks for your response.

[DBerry]

I believe the NI9476 has a propagation delay of 500microsec (see http://sine.ni.com/ds/app/doc/p/id/ds-173/lang/en).  This is the time it takes the signal to reach the outputs of the module.

Also, the maximum update rate is 40 microsec so if you write to the outputs faster than this, the module may miss data.

Dan