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FPGA set up baud rate NI-9853

HI everybody,

I have a CRIO-9014 and a module NI-9853 and I work on these from few days. I have a problem with a set up of baud rate of Port 0 and Port 1 through the FPGA VI. I attached a picture of my current VI. The goal is to have a possibility to change the baud rate of port 0 and port 1 in real time during the execution of FPGA VI.

I have read many posts on this problem but I do not find ad real answer. Can you help me and show a picture of a correct VI?

 

Thank you very much 

FPGA_Setup_BaudRate.jpg

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Hi,

this document explains how to set 9853 baud rate programmatically. You can find also more details here.

The same property you are setting is used.

Thus, what is your exact difficulty? Isn't the VI working correctly? Are you getting an error?

Bye,

 

Licia

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Hi Licia,
thank you for the links but I just knew their. The first problem that I have to solve consist in change the baud rate of port 0 and 1 of NI-9853 through the RealTime VI and, obviously, read and write the data. I saw and tested the three block that allow this but maybe the position of their is not correct because the result is no good.

Can you show me the right position in a VI in order to change the BaudRate from RealTime VI with the blocks that allow to read and data shown in my image?

Thanks

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One or two things about your picture from the first post:

  1. You are stopping, setting baudrate and starting the CAN card for every loop iteration. This can cause the CAN card to drop all the recieved CAN messages there is in the queue in the CAN controller. You will then loose ALL the messages.

    Make sure you are only changing/setting the baudrate when the baudrate is actually changed.
  2. As the code is now, you will only see the latest CAN message on the bus, and not all. Are you sure that is what you want.

 

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Thank you DKFIRE for your answer. Below it is possible to see the new version of FPGA's VI. Now it is correct?

The numbers that I have to insert in the BaudRate control are:

 

-125,500,1000

or

 

-125000, 500000,1000000

 

because the common baudrate are 125kbits/s - 500kbits/s and 1Mbits/s

 

thanks

FPGA_Setup_BaudRate2.jpg

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