FPGA resources

[jyang72211]

When I look at my compilation report for my FPGA code on a PXI-7833R.  I see teh parameters below.  They are all listed individually.  However, I thougth a slice consists of register and LUT, isn't it?  Does Slice Registers and Slice LUTs just further explain Total Slices?  If so, I don't see how the math works out in my attached compilation report.  

Total Slices

Slice Registers

Slice LUTs

Block RAMs

[Intaris]

On your target a slice consists of two LUTs and two registers.

Each family of FPGA chip has a different slice composition.

Shane.

[alcava.cr]

Hi,

Here are a couple great articles that will help you understand better the concepts:

1. What is the Definition of Logic Cells, Logic Slices, Configurable Logic Blocks and Gates in Reg

2. Introduction to FPGA Hardware Concepts (FPGA Module) - LabVIEW 2011 FPGA Module Help

3. FPGA Fundamentals

To add a little more information…here you can see which FPGA is inside of your target (Virtex-II in your case). If you have specific questions about the architecture or composition I can recommend looking at the Data Sheet. 

I hope this helps

[jyang72211]

that doesn't answer my question at all.  I just needed a yes or no.  See below.  I think the answers are Yes, but just wanted to be sure.

‎03-08-201408:28 PM

When I look at my compilation report for my FPGA code on a PXI-7833R.  I see teh parameters below.  They are all listed individually.  However, I thougth a slice consists of register and LUT, isn't it?  (Yes or No)  Does Slice Registers and Slice LUTs just further explain Total Slices? (Yes or No)  If so, I don't see how the math works out in my attached compilation report. 

Total Slices

Slice Registers

Slice LUTs

Block RAMs

[jyang72211]

When I look at my compilation report for my FPGA code on a PXI-7833R.  I see teh parameters below.  They are all listed individually.  However, I thougth a slice consists of register and LUT, isn't it?  (Yes or No)  Does Slice Registers and Slice LUTs just further explain Total Slices? (Yes or No)  If so, I don't see how the math works out in my attached compilation report. 

Total Slices

Slice Registers

Slice LUTs

Block RAMs

[jyang72211]

I did see that, but that's what doesn't make sense.  Referring to my previous attachment, , 15880 slice registers, 18141 slice LUTs, and 13692 total slices are used.  If one slice contains 2 registers and 2 LUTs, total slice should be the bigger of the two (slice registers or slice LUTs) and divide that number by 2, right?  In my case, I should divide the slice LUTs by 2 to get total slice, but the math doesn't work out.  Why is that? 

[nathand]

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@jyang72211 wrote:

I did see that, but that's what doesn't make sense.  Referring to my previous attachment, , 15880 slice registers, 18141 slice LUTs, and 13692 total slices are used.  If one slice contains 2 registers and 2 LUTs, total slice should be the bigger of the two (slice registers or slice LUTs) and divide that number by 2, right?  In my case, I should divide the slice LUTs by 2 to get total slice, but the math doesn't work out.  Why is that? 

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Because you're assuming maximal usage of each slice, but many slices may not be completely utilized. For example you might have some slices in which one register is used and the rest is unused.

[jyang72211]

So the total slice figure should be what I am looking for in terms of capacity, right?  Let's say that i have 

total slice: 100%

slice register: 60%

slice LUTs: 60%

i should conclude that my FPGA is full, even though some slices are not completedly uttialized.  There is no way to make the FPGA uses these partial slices, right?  

[nathand · Accepted solution]

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@jyang72211 wrote:

So the total slice figure should be what I am looking for in terms of capacity, right?  Let's say that i have 

total slice: 100%

slice register: 60%

slice LUTs: 60%

i should conclude that my FPGA is full, even though some slices are not completedly uttialized.  There is no way to make the FPGA uses these partial slices, right?  

---

No, still not quite right. The FPGA compiler stops optimizing once everything fits and meets timing (or it determines that there is no possible way for everything to fit). If you add more logic to your design, the compiler might be able to make it all fit, although the compilation will take longer.

Even more confusing, if you're just on the edge of what you can fit, sometimes the compile will succeed and other times it will fail for exactly the same code, because the compiler (really the place-and-route step) uses a random starting point for placing logic.

For a very-simplified analogy, let's say you have a collection of triangles (registers) and squares (LUTs) that you want to fit inside a piece of paper. If you only have a small number of triangles and squares, you can put them anywhere. As the numbers increase, you need to arrange them to pack them more tightly, and when it starts to get very tight you might have to try several times to get everything to fit. That's what the FPGA compiler is doing, with additional restrictions on where logic can be placed due to timing requirements.

[jyang72211]

If i understood you correctly, my example (see attached) still have plenty of room in the FPGA.  If I do add more logic, it will fit but the compile time will increase, right?

[nathand]

Unfortunately, you can't know until you try it. You definitely don't have "plenty of room" but you probably do have some room. You will almost never achieve 100% utilization of the FPGA because registers and lookup tables are not completely interchangeable from one slice to the next. If you have a design in which there is exactly one lookup table available, and you add a function that requires exactly one lookup table, the compile still might fail, because that lookup table isn't in the right place to connect to the inputs that feed it and the outputs that it drives. The compiler generally tries to keep related logic close together (on the same slice as much as possible) and avoids putting unrelated logic together (don't put the registers for one function on the same slice as the LUTs for another if it can be avoided). Each slice only has a certain number of connections to other slices, and in order to meet timing, signals can't travel too far across the chip. You might have logic space available on the FPGA but it could be in the wrong place, making it unavailable. (Side note: it constantly amazes me that the compiler has to account for the amount of time it takes an electron to cross the chip, but that's more or less what it's doing. I'm not an electrical engineer so if you really want to learn about propagation delay and fan-out, find a coworker who is knowledgeable about such things, or hope that someone contributes more details here on the forum.)