FPGA: "The bitfile signature does not match." No Changes Made

[James.M]

Hello,

I have a project involving a cRIO9082 and its FPGA Target. My problem is that I keep having to recompile the FPGA build even when I haven't changed anything. Is there a setting that I'm missing here?

Thank you,

[PiDi]

When exactly you're asked to recompile the VI? When running FPGA VI directly or when trying to run it from FPGA Interface on RT/PC? 

[James.M]

My RT code throws an error telling me to recompile when it tries to initialize the FPGA.

When I click the build in my project and select "Check Signature", I get the message "The bitfile signature does not match."

[PiDi · Accepted solution]

OK. It's hard to say why its need recompiling, but the quick workaround is here: configure Open FPGA VI to open bitfile, not the VI (you'll need to create Build Specification on FPGA, build the VI into bitfile).

As for the reasons why it needs recompiling each time:

- Are you moving this code between different machines (via source control for example)? Different version (SP) of LV or FPGA module can be the reason.

- Are you making any changes in the subVIs of your main FPGA VI?

- Do you have any VIs that are used both on FPGA and RT?

[James.M]

Thanks for the advice! I forgot about the Open FPGA options. Hopefully that will work for me. I'm recompiling now and will try to recreate the error once finished (Cloud Compile is a lifesaver).

-I'm not moving code between machines.

-I haven't been making any changes to any FPGA VIs and, actually, I've been leacing that chassis section collapsed.

- All of my FPGA VIs were created seperately from the RT VIs. There aren't very many, so this wasn't too hard to keep track of.

Thanks again,

[KHartley]

Hey James,

We from time to time see vis that need to be recompiled when they are open and refer to them as dirty dots. If you can trace down which specific vi(s) in your fpga keeps causing the vi to mark as changed we'll create a car to have it fixed. 

Using the bitfile should mitigate this issue for your but we'd certainly like to find out what is causing the change for you and have it fixed.

[James.M]

Will do!

[JonP]

"Will do!" - and did you? If so what did you find?

I am having similar problems using LabVIEW 2017 with a very simple FPGA VI that uses little else, and came across this thread with a search. When  I copy the lvproj to the same path to an identical system I am told that the bitfile signature does not match. It would be good if NI could give a description of exactly why in the error message, i.e. tell us which "dots" are "dirty", then we would know what to fix and wouldn't have to do internet searches!

[Intaris]

Sometimes just changing a conditional compile structure back and forth can provoke this.  Some changes (I think) simply get marked as "changed" without actually linking to how it was beforehand meaning that a change to something else and back again remains marked as "changed".

This causes us all kinds of pain when we re-use VIs on FPGA, RT and host because any conditional compile structures cause the VIs to be almost permanantly "dirty" event hough with regard to the single target, they haven't changed at all.

I try my best to avoid conditional compiles for this reason.  But even a difference in DMA configuration int he project can be enough to trigger this.  It's quite annoying.