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FPGA problem with fractional decimator

So I'm writing an application base on the NI scope 2014 instrument design libraries. I'm trying to simply replace the integer decimator that is used in the design with a fractional decimator from the palette. The design seems to work running in simulation mode, with values being streamed to the PC host. However when I try it on the physical hardware (5170R) the acquisition times out. This happens even if I give it an extremely long timeout- basically no samples appear at the PC end.

 

I suspect that the problem may have something to do with the fact that the decimator requires a x3 clock. After creating a x3 clock in project explorer (it's a pre-existing option from the new clock menu), when I look at the clock properties, there is a warning that LabVIEW will not generate a clock period constraint for this clock, which must be defined in a CLIP file. I assumed it would be OK as it is derived from a pre-existing x1 clock in the project (which also has the same warning but presumably 'works' as it's used for the sample loop).

 

Any ideas?

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