FPGA or Real-Time App?

[rberger]

Hi everyone:

In my next application I need to generate a constant 40Hz pulse train whereby I need to be able to give it a variable duty cycle within a 25ms window. In programmer speak, if I have 1D array of duty cycles, I need to be able to index the array element, load it into the the hardware with the new duty cycle within 25ms and ensure the hysterisis between old pusle train and new pulse train is within 25ns. Now, I know Windows XP cannot give me deterministic 25ms resolution (or can it?) for loading the new duty cycle value. What hardware should I use to ensure my timing requirments are met? FPGA, Real-Time or both?

Thanks
Robert

[Christian_L]

It sounds like you are generating a 40 Hz PWM (pulse width modulation) signal. I can think of two general options.

1. LV RT and a counter timer card (e.g. 6602/6608). The card can generate a very stable signal and you can update the pulse parameters (length of the high and low phase) from your host application (LV RT). The transition from one duty cycle to another will be seamless. However the card can not store an array of duty cycles. You will need to update the card with the desited duty cycle (pulse widths) each time. The 25 ms requirement to update the duty cycle is relative to what other event? i.e. what will cause you to update the duty cycle being generated.

2. The second option is to use a FPGA/RIO card to generate the PWM signal. You can
store the array of duty cycles in memory on the FPGA and then just index the array form your host application. It will take about 1.5 microseconds to change from one duty cycle to another controlling this from a LV RT application.

Christian L

[rberger]

Thanks Christian:

That 1.5 microseconds to change from one duty cycle to another is in a spec somewhere for the FPGA solution or did you measure it?

Thanks
Robert

[Christian_L]

That is based on the time it takes to write a new value from a host application to one of the registers on the FPGA. The FPGA will use the updated value on the next cycle of the PWM signal. The value is based on benchmarks I have performed (LV RT running on a PXI-8176 controller).

Christian L