FPGA loop time optimization - CRIO 9082 - 9224 analog input module

[JFBerlemont]

Hello,

I'm fairly new and unexperienced on FPGA.

I'm using a cRIO 9082, with some high speed data acquisition module, like 9224, which is supposed to operate at 1 MHz sampling rate.

I need to read data on some analog input of the 9224 and react within microseconds, based on a fairly simple algorithm.

I have isolated the communication with the 9224 module is a separate loop, focusing only on this task, and storing the read value in an indicator. (see annexed picture)

But just this loop, seems to run at maximum 3 us per loop. It seems it does not approach the 1 us per loop I was expecting. 

what is the reason why this loop does not run faster than 3 us per loop ? What are the ways to bring it to 1 us per loop, as the 9224 module is supposed to run at 1 MHz ? I'm probably missing something because I'm not experienced enough on FPGA. Any help will be very appreciated.

J.F.

[Jacobson-ni]

I'm guessing you're actually using a 9223 and not a 9224 is that correct?

Aside from that, the obvious thing to check for is that the loop timer is configured correctly. The VI isn't attached so you will have to tell us how the loop timer is configured and how you know the loop timer local variable being used as the input is the value that you are expecting.

[JFBerlemont]

Hello, and thank you very much for looking into my concern.

Yes, of course, this is 9223 module, not 9224. Sorry about that. 🙂

I'm using 3 different independent loops to communicate with various modules. I'm using another 9221 for low speed analog input (approx. 10 us loop time rate), and another to output to a 9401 for the control of our device. On each of these loops, I'm using the same timing measurement block. Finally, I have another loop that computes the output based on inputs, settings and history (more complex algorithm). This loop also has some timing structure in the same way. One of the output of this experiment is to evaluate the efficiency of control, in function of the loop rate, in order to define the future hardware that will run this process. (this is for fuel injection control ECU, on diesel engines).

Therefore, I have control on the loop rate I want to have for this part of the process, and I monitor what I really can obtain. If I ask for 10 us loop time for the global monitoring process, I get 10 us feedback for all loops (except the low speed data acquisition on 9221, of course, limited to approx. 8 us by the 9221 hardware) . If I ask for 3 us, I do get 3 us for all parallel loops. But when I go below 3 us requested loop time, I get it for all loops, except the input on the 9223 module, which seems to be blocked at 3 us. And this is precisely the question I have. Why is it blocked at 3 us, and what are the possibilities to go below that, towards 1 us which is what I was hoping ...

Thanks in advance for any support.

J.F.

[oscarfonseca]

JFBerlemont, why don't you try benchmarking how much time (or clock ticks even) does the Analog Input block takes for your code?

This way, you can check if the ADC is being able to acquire at the requested speed with the clock you are currently using. I also suggest you benchmark it without a front panel indicator wired to it, as it can create some overhead time after the reading from the I/O node.

Let us know your results.

[CFER_STS · Accepted solution]

The specifications on the NI 9223 datasheet indicate a maximum sampling rate of 350 kS/s using FPGA IO nodes, which corresponds to a period of 2.857 us.

You can speed this up to 1 us acquisition by separating acquisition and data transfer using User-controlled I/O sampling:

https://knowledge.ni.com/KnowledgeArticleDetails?id=kA00Z0000019Km2SAE

[JFBerlemont]

Hello,

thanks for the suggestion. I believe I'm doing basically the same thing with the code I have (see annexed picture in the first post), and this returns as effective rate a minimum value of 3 us, can not go below that, no matter what I put as requested rate. Therefore, the time taken for the acquisition is 3 us ... Am I wrong ?

This seems to be confirmed by another reply, which indicates that the spec of the 9223 says that using FPGA IO nodes, the fastest execution time is about 3 us ... It may look like I could be limited at this maximum speed ...

J.F.

[JFBerlemont]

Hello,

thank you for your response.

It would explain the symptoms I have with "being" blocked at about 3 us loop time.

I will try the user controlled IO mode, and come back to you with the results.

Thanks.

J.F.

[JFBerlemont]

It works fine with this solution.

Thank you very much for your help.

I have annexed the updated part of the code which allows me to capture data at the expected rate of 1 MHz.

I first forget to add the 4000000 constant as input to time out, and it did not work (acquisition of a lot of zeros), but with this constant, it works fine, up to 1 MHz.   Thanks again.