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FPGA high frequency decimation

Hello all,


I would like to decimate the output of a 50 MHz 16-channel module (5751B) to something around 10 MHz. Ideally I would like to average 5 samples on each channel input and produce one sample for each output.

It looks like something the "Rational resample" VI would be perfect for, but I can set it up for such high frequencies.

I was considering manually doing it by averaging samples in a SCTL and outputing only every other 5 iteration but I can't think of a way to code this properly. Any suggestions?

I am using LabVIEW 2016 on a 7972R target.


Thanks in advance!

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I would use the functions in C:\Program Files (x86)\National Instruments\LabVIEW 2018\instr.lib\_niInstr\DSP\v1\FPGA\Public\Sub VIs\HB Decimator

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If you wanted to do it yourself, I suspect given the FPGA limitations you'd probably want to do something along the lines of:

  • Have a shift register on your SCTL with an integer, select on Equals 5, increment each value and reset to zero (need to check after incrementing, or else you'll get 1/6 values, not 1/5)
  • If true, output the sum via FIFO or whatever you're using. At the other end (on the host) divide by 5 in a floating point number. (See note below)
  • If false, add to sum (in separate shift register)

suspect you can store a 16 element array in your shift register and add all the values at once. If not (I haven't used 2016 FPGA, but I'd hope this would work) then you might need to index the 16 elements, and have 16 separate shift registers, and duplicate the code 16 times.


You may also need to write to something like VI-defined block memory and have a While loop output to the FIFO (or setup handshaking and pipelines?) since you can't write 16 values to a FIFO inside a SCTL and doing this every 5 cycles, you can't even use the same loop I guess (maybe you already have channel-specific FIFOs?). In any case, perhaps you've already handled this issue?

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Message 3 of 4

Thank you both for your replies.


cbutcher, that's exactly what I was looking for. Your message made it clear in my mind, and I think it will work fine. I was unsure about how to output the sum only every 5 iterations, but I just realized that I can wire the "input valid" of the FIFO write to make it work. I haven't tested it yet but at least it compiles for my target, with the 16 element array as a whole in the shift register.


I will post updates when I can confirm that it works as planned.

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