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FPGA forced compilation at the least modification: Is there a way to refuse it?

Hello!

 

Every time I'm making the least code modification (with or without saving), the IDE refuses to execute without a new compilation

 

 

This is a problem, because: it makes me lose time recompiling everytime I have the slightest modification to do/validate;

 

and worse: if I'm accidentally changing something (add a boolean, then undo) during compilation, I get the following message at the very end of it : "error! source code is different than compiled source" and so, I have to restart a build.


I've been told that in standard text compilation IDE, the user can choose to compile the current modification or keep what is in FPGA memory executing.

 

is it possible here?

 

regards

Pierre FKAIZEN SOLUTIONS, Grenoble
Certified LabVIEW Associated Developer

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It sounds (to me) that you might be initiating the Compilation with the FPGA "open", perhaps by clicking on the "Run" button.

 

If you want a safe way to "examine the FPGA, including moving wires, etc." but not force a new Compilation, simply close the FPGA VI without saving it.  Once it is closed, go to its Build Specification and select Rebuild.  As I recall (and you should check this, as I'm writing this "off the top of my head" (where there's not enough hair to keep the ideas inside), there's a subtle difference between "Build" and "Rebuild", and I think you want the latter here.

 

Bob Schor

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This happens in only a subset of possible configurations:

Are you executing the VI in interactive mode? i.e. FP visible on the FPGA?

Have you linked your "Open FPGA Reference" to a VI or to a Build Spec?

Any of these will tie the exedcution of your FPGA to the CURRENT state of the source code. And yes, do / undo will cause a "dirty dot" and make the compiler think the code has changed.

 

Try linking it to a bitfile instead.

 

This will decouple the last compilation from what your code represents.

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As Intaris said, the behaviour you sound like you want is opening a bitfile, rather than a Build Specification or VI.

 

Something like the following would do what you want:

cbutcher_0-1635492035860.png

 

(Of course, the Run tickbox you should change depending on your needs).

 

 

Spoiler

You can also "Bind" the reference to a typedef to make it easier to update VIs that use the reference later.

Note that this will mean that if you change what the reference would reflect (e.g. you add a new FP control to the FPGA main VI) then you have to recompile to get a reference that contains the control.

 

If you want to develop the RT/Desktop side whilst it's compiling (or before submitting a compilation, but after making changes), you can switch to the VI/Build Spec options temporarily to update the typedef, and then switch back when compilation finishes.

 

If you do that, be careful to consistently set the bitfile you need and make sure the typedef rebinds after the compilation finishes, sometimes I've had weird behaviour loading bitfiles in this sort of setup.

 


GCentral
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