FPGA execution mode

[igbaquedano]

Hello all.

Before writing about my problem I will try to describe my application and what I want to achieve. I have an sbRio in which I want to implement a control algorithm in order to control an inverter. At the moment, I have two main loops.

First loops read grid voltage from 3 analog inputs and it allocates them in a memory (with look-up table implementation). Execution time of this loop is 400 tick (I use tick timer VI for that).

In second loop I read from memory grid 3 voltages and I calculate wave phase and frequency with a PLL. Execution time of this loop is 400 tick as well.

In order to test this set up, I select simulation execution mode first. Instead of saving analog inputs in first loop, I simulate a grid with a VI. When simulating everything works fine and frequency and phase is correctly calculated. When testing with the real hardware it does not work. I think the problem is in how I pass voltage information from one loop to another, but I am not sure.

Hoping anyone can help. Thank you and best regards!

[Intaris]

I think it's because the quantum oscillator in your phase-declined-subwoofer are not compatible.

Jokes aside, please post an image of your code or even better, the code itself so that we have any kind of idea what you're talking about.

I think the problem is in how I pass voltage information from one loop to another, but I am not sure.

Don't you think then that a few words about HOW you are doing that might help identifying the problem?

[igbaquedano]

Sure. I upload the code. I also upload the vi I use to simulate the grid.

Regards.

[JensG69]

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@igbaquedano wrote:
I think the problem is in how I pass voltage information from one loop to another, but I am not sure.

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Yes, that IS your problem. You programmed a classic race condition by using a memory method for the data exchange. It would have been the same if you used three global variables.

Your two loops are not synchronized so you never know when results will be written to your memory and when data will be taken from that memory.

I suggest that you switch over to a FIFO method and add a "delimiter" channel so that you can distinguish between different data sets on the read loop.

Regards, Jens

[igbaquedano]

Thank you for the advice Jens.

When it comes to synchronization, what method would you use? Would you deal with occurrences or is there anything more efficient?

What do you mean by a "delimiter" channel in FIFO. Do you mean to use interleaving?

Best regards.

[JensG69 · Accepted solution]

Here is a (draft) screenshot of my idea.

Top loops: Upper loop represents your aqusition loop, data is transferred by FIFO to the calculation loop. In order to syncronize the loops I have added an additional element that gets transmitted. The value of this additional element should be chosen in such a was that it is an invalid value for the normal aquisition. The calculation loop can then look for that sync value.

Another idea, shown in the bottom loop: Why do you split your problem in two loops. Both loops take the same time, so do the aquisition and the calculation in parallel inside one loop.

Regards, Jens

[igbaquedano]

Thank you very much Jens.

Your explanation was very clear and helpful I will apply what you suggest with FIFOs. Anyway, with the synchronization you showed me in the first example, could it be possible to use a memory instead of a FIFO? There will not be any more race conditions right? What would be the advantage/disadvantage of FIFO vs Memory?

Could it be correct to use occurrences (to synchronize both loops) and memories (image attached)? Would this avoid race condition?

The reason why I split acquisition and calculation in different loops is because in the future I will need to run them at different speeds.

[JensG69]

Hello,

your idea might work, but I strongly recommend to set the occurence either after the FOR-Loop or on the second or third write cycle (depending on how fast memory read and memory write are definded) and not in parallel to the FOR-Loop.

Regards, Jens