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FPGA derived clock with lower frequency for simulation

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I am simulating some FPGA code for an sbRIO-9607, and the lowest frequency derived clock I can create is 5MHz (limited in the IDE, presumably based on PLL divider limitations of the Zynq-7020).

 

For certain tests my simulation is running too slowly and I would like to trade time resolution for speed. Is there a good way to create a derived clock that runs slower than the minimum derived clock frequency, but only for simulation purposes? I am simulating my code using an FPGA Desktop Execution node within a Control & Simulation Loop.

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Hello shansen1,

 

I think you can try to do it inside your program placing a Tick Count to control how many ticks you need from the base clock to get the clock speed you need. It's maybe not the best way but for Simulation purposes it seems right.

 

The logic behind depends directly on your application's purposes but it comes to my mind that a Case structure with a Quotient & Remainder will do it. If you share your code I could give you a more specific advice.

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Pedro_Rojas: thanks for the reply. I have been thinking about this problem over the past week, and the problem is that I make heavy use of SCTLs for timing. For example:

 

SCTL.png

 

This SCTL is used to generate a sample clock that other pieces of code trigger on. Because this loop runs at the top clock rate, and I can't create a clock slower than 5MHz, I am effectively stuck with a 5MHz update rate for this loop.

 

I think the only other way to accomplish this would be to change the SCTL to a normal While loop with a Tick Count (using a conditional disable so it would go back to an SCTL when not in simulation), but that is a rather large change as I would have to fully duplicate the code in the SCTL within the while loop, and any time I made changes to the SCTL loop I'd have to copy it to the While loop and vis versa.

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There is another way that is using an external clock. For doing this you need to have an FPGA that accepts this and a way to check it is trying to follow this link http://zone.ni.com/reference/en-XX/help/371599E-01/lvfpgaconcepts/external_clocks/ and see if you don't get any warning nor errors.

 

I think you would be able to generate the clock using the sbRIO.

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