FPGA dataflow and error handling best practices

[drummaniac83]

I'm looking into using FPGA for some large projects and wanted to get fellow users opinons on dataflow vs sequences and general error handling best practices with labview FPGA....

Doesn't seem like NI deals with this topic in depth for the nuances of FPGA.  Taking a cue from hardware, I am considering a error "register" indicator U32...using error in and error out with a simple U32 for error codes instead of a full error cluster.  Cluster seems like it would be too resource hungry for FPGA.  I could then use the U32 for dataflow order of execution control vs having to have sequences for a more natural labview programming style.

Anyone thought about this much or does every just use sequences and error clusters?

Josh

I'm being told to mention I'm a CLA.....not into dropping titles, but perhaps this will help set the baseline on the complexity of discussion we can have

[nathand]

For sequencing, my FPGA code tends to rely heavily on single-cycle timed loops (SCTL) structured as state machines wherever possible, to get the performance and space benefits. I don't use error wires in my FPGA code and I don't check the error out terminal from method nodes because of the extra FPGA space required, unless I'm actually concerned about the error value. I would rather use a sequence structure to set execution order in FPGA than use a wire that consumes resources to store data that I don't really care about. That's my approach - does that help? If you have a more detailed question I might be able to provide a less generic answer. I like to think of the FPGA as hardware where nothing should go wrong, and if there is an error it's catastrophic (bad hardware) and not something that software can handle. Your application might be different, though.

[drummaniac83]

Nathand,

thanks so much for the response.  It definitely answers some questions for me. I am kind of adopting the code and the previous developer used kind of an adhoc method of development. 

Now there is a push to get the code more maintainable and reusable, and also questions about how to minimize integration time (more effectively debug).

Obviously, in regular labview the idea of a sequence structure is usually frowned upon, but my experience with FPGA is that a lot of the "bad" things in Windows Labview are not "bad" on an FPGA (build array, sequences, etc)....you comment on sequences vs wire makes perfect sense from a resource perspective.  My main goal at first is to just make it more readable, modularize some of the redudant code and improve the documentation.