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FPGA data acquisition - dropping samples

Hi

 

I am trying to store a sampled sinuosidal signal, just streaming data without any processing neither over FPGA nor the host. I am using NI-5761 digital adapter for acquiring the analog signal and NI PXIe-1071 chassis that has both the FPGA and the host running Windows-7.

 

According to the system specifications, it could run up to 250 MSPS. However, my main problem lies in dropping samples over a wide range of sampling frequnecies even 1 MSPS and of course any other higher sampling frequency !

 

You can find attached the FPGA and Host VIs, Fifo_TargetToHost.vi and Fifo_Host_SaveOnly.vi, respectively.

 

As you can see in the Host VI, I removed any kind of prrocessing so just streaming data and storing it in a text file. For 1 MSPS, using Target to Host FIFO of size 8192 and FIFO at the Host of size 50000, I get a distorted signal. You can find a snapshot attached "distortedsignal".

 

So, is it a common problem or I am missing something in my system setup or configuration ? please If I am missing any information that could help, tell me.

 

Thanks.

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Hello!

 

First of all, I'd like to apologize for my delayed response. There was a problem with the notification I received and I was not able to post back until now.

 

I looked through your code and there are a few things that may be causing this problem. Firstly, I noticed that you are reading the data from the IO node, you are writing it to a target-scoped FIFO, reading that FIFO in the same loop, and then writing the data to the host through a DMA FIFO. I am not sure why you are using a target-scoped FIFO. You should just read the data from the IO node and write it directly to the DMA FIFO. If your are using this FIFO as an additional buffer, I would transfer the data to a second loop and then to the DMA FIFO vs. doing everything in the same loop.

 

Additionally, the way you are doing the File IO operations is going to present a problem. The VI you are using is considered one of the "high level" VI's which means that it is doing many operations within itself. In this case, every time you call the VI it opens, writes to file, and closes it. As you can imagine doing these three operations every iteration of the loop is very slow. This can cause the DMA FIFO to overflow as you are not able to read fast enough. For best performance I would do tow modifications to the file IO operation. Firstly, I would implement a producer-consumer architecture and use a queue to send the data to a second loop. In this second loop, use the low-level file IO functions to both open and close the file outside of the loop, and only write to the file inside the loop. These two modifications should allow the code on the host to run much faster, which will prevent the DMA FIFO from overflowing.

 

Please let me know if you have any additional questions.

 

Regards,

 

Eli S.

Applications Engineering

National Instruments

Eli S.
National Instruments
Applications Engineer
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