FPGA compile problems, FPGA loop size

[1hdsquad]

I developed an application running on a realtime desktop pc, now I need to port the application to a small cRio 9074. On the FPGA part I want to run some array calculations. After adapting the vi to FPGA restrictions (fxp...) I had no sucess compiling it. Both trials on an Intel i7 with 8Gb RAM stopped after 2-3 hours, first error was a process blocked and needed by the compiler, on the second run it reported not enough memory.

I want to test the cloud compile option to see if the vi compiles there. Apart from this Im afraid Im doing something stupid in my code which simply is too much for the FPGA. Im not allowed to post my code here so Ill describe what it does.

Ive got two 1D arrays of the same lenghts (~500 elements each). A hand full of for-loops performs operations on them. Some depend on the previous iteration, others dont. Some of the later loops could run in parallel. In the end I receive some scalar values.

Is this concept feasible in the FPGA or is this the cause of impossible compiling? Does the compiler try to implement a few thousand parallel loop executions? How do I find out whats wrong?

[GerdW]

Hi,

instead of using such big arrays on the FPGA it is recommended to use memory blocks!

For more advice you should attach your VI (or atleast a picture of the BD) and give a description of your algorithm…

[ToeCutter]

What Gerd said. But to add...

FPGA programming is fundamentally different from programming a PC. Don't be fooled just because you're presented a common graphical interface by LabVIEW.

To expect to write FPGA code with no training or study is absolute folly. Do yourself a favour and find a course. You may be entitled to free self paced training courses from NI depending upon your license.

[1hdsquad]

You are right, though I know the differences between FPGA and conventional processors, Im learning VHDL on the side and I already received the course documents for Labview FPGA, Im working myseld through.

The arrays contain 2D sensor data, the data is refreshed every 10ms. The data gets filtered and abstracted so I can get my results. How does block memory help me here?

[Hooovahh]

An array of data on the front panel, is stored in very different ways then a look up table, and very different from Block Memory, which is also very different from storing it as DRAM.  Here are a few articles

http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgaconcepts/fpga_storing_data/

http://zone.ni.com/reference/en-XX/help/371599J-01/lvfpgaconcepts/fpga_array_memory_implement/

I was told by a former FPGA R&D guy at NI that when an array contains more then 32 bits of data on the front panel, the amount of needed resources to store it grow exponentially with each new element in the array.  

So say you have 32 booleans in an array.  We will pretend it takes up 10 gates.  To add that 33rd boolean it could take 10 gates more.  Adding a 34th could take 20 gates more.  He described it similarly with numbers.  If you have 4 U8 numbers in an array it takes some amount, but takes much much more to store a 5th U8.  You trying to store 500 anythings in an array on the front panel just can't be done this way.  That's why you need to use one of the other memory storage elements on the FPGA.

[1hdsquad]

Thank you Hooovahh!

Its hard to find those answers in the manuals and documentations when you dont know where to start and without a feeling what you are doing wrong. They show you like temperature controls on a FPGA but nothing serious... On the other hand I think its frustrating that labview allows me to do this BS and never warns me...

Generally speaking which method do you recommend to get big amounts of data into the FPGA cyclically and out again? Lets just pretend I wanted to do something like image processing, 30x30 grey values.

Which methods are worth trying?

[ToeCutter]

I recommend a pair of FIFOs. One to write, one to read. You'll need to flatten your arrays to pass them through. Look up multiplexing and demultiplexing for an idea how to do it.