FPGA compilation stops at "Synthesizing: Report RTL Partitions:" with 0% CPU cost

[jiangliang]

Hello:

I meet a problem when compiling my FPGA code:

It stops at Synthesizing, and the xilinx log stops update at :

Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------

In task manager I can see the vivado is not doing anything right now.

I'm working with FlexRIO 7935， LabVIEW 2018 f2

In my code i'm using DRAM with some BRAM (about 25%), and some host to target/target to host FIFO, as well as some DSP48, code write in two clock domain, DRAM clock and 40M Clock.

If I put all code in DRAM clock domain, it actually compiles, but with DSP48 fail to meet the timing requirement,  so I use a FIFO to separate DRAM operate and process code, and it here I meet this problem.

I already checked my system is working, I can compile blank VI, as well as some other simple VI.

Any advice? Thanks!

[jiangliang · Accepted solution]

OK，I get the problem.

I should not put Input or output terminal in DRAM Clock domain.

I'm now using register as a buffer, things works.

Nonetheless it is a bug NI should look into, I think many might be confused when face such problem, the error simple didn't provide  any information on it, and LabVIEW doesn't have any mention about Input/Output should not put in DRAM Clock Domain.

[jiangliang · Accepted solution]

One more thing.

You should not put a Host to target FIFO status node in DRAM Clock Domain SCTL, you can not finish compile the code, also, you won't know any detail about why it fails.