I am using NI 9215 to acquire and log six number of signals.Therefore I am using 2 NI 9215 modules. three signals are in the range of +/- 1V and other 3 are in range of +/- 5V. I am using FPGA based (DMA) data transfer and in the RT side I am logging it to a spreadsheet file, using "merge signals" operation. I am logging 65000 data points each channel. The frequency of acquisition is same @ 12.5kHz. My problem is there is cross talk between channels ie: data in one channel appeard in the other and vice versa. I tried single FIFO and multiple FIFO options, ie: 2+2+2 channels respectively into three FIFO's. Neither single nor multiple FIFO's are eleminating the problem. My signals are single ended and referenced to the ground. All -ve's of the 9215 are grounded to the power supply ground, and it is also connected to the ground of the module. Positive screw terminals are connected to the AC signal. Please suggest how to eleminate this.
Attached is the vi architecture i followed(for single and multiple FIFO's.
I suppose your 9215 inputs are connected with high impedance and therefore too sensitive. Put a 100k load to your AC signal to check this. (Haven't checked your sources)
The signal is coming fine. Actually the cross talk is random, in the sense, suppose I log 3 channels data, say I log 20,000 pts, then some files it comes at some places, in some files it do not! I have been trying my best to solve it, but 2 months i have already wasted on this...! Please suggest me some solution.
* Edit - just had another look at your diagram and you seem to already be de-interleaving. Apologies!
When you write multiple channels to a DMA FIFO the data is interleaved. In order to reorganise the data you must 'de-interleave' it.
This is also covered in the cRIO Developers Guide.
Hope this solves your problem,
One suggestion, you could place an indicator to check you are always reading the same amount of points for the DMA FIFO on each iteration, the RT and FPGA might be out of sync.
You could look at using interrupts to sync the RT and FPGA if that is the problem. That's also covered in the cRIO Dev Guide.
Have you also checked to make sure your FPGA FIFO isn't timing out (i.e. you aren't reading fast enough on the RT side to keep up with how fast data is being added). Overflowing FIFOs could be screwing up your data also
If there's no real hardware crosstalk, I suggest you to read your data always in multiples of 6, so data can't be interchanged.
btw: I'm not really sure that you can set FPGA IO nodes (your parameters) before actually running the FPGA.