FPGA: User controlled I/O sample pulse generation in SCTL

[riplakish]

Hi guys,

I'm using a 9222 AI module in a 9064 cRIO to try and do user controlled sampling at around 8kHz.  I would like to be able to generate the sample pulse for the 9222 from within a SCTL which I'm using to generate PWMs and some other things, but when I go to compile I get an error which says that the Generate I/O Sample Pulse Function is not supported inside an SCTL.

This seems contrary to what I read in the help article here, which states that "This node is supported inside and outside the single-cycle Timed Loop if the target supports it."  Maybe it would work with a different FPGA target?  If so I can't find a list of devices supporting this. I've been able to implement the pulse generation from a while loop, but I'd really prefer to use an SCTL if possible. Thanks for the help.

[dmysliwiec13]

You will need to look at your hardware's specific documentation. here is a link to a support manual that explains where you can find this information. 

FPGA Target Hardware Documentation (FPGA Module)

https://zone.ni.com/reference/en-XX/help/371599G-01/lvfpgahelp/fpga_target_docs/

- Danielle

[riplakish]

I tried to follow the LabVIEW help directory given, but there is no topic called "CompactRIO Reference and Procedures" under FPGA Module in my Contents tab.  I notice that the page says "You must have support for the FPGA target installed to access the target-specific documentation.", but I'm not sure what they mean by "support".  I have the FPGA module and the device drivers installed if that's all it means.

Going back to the original question, I'm not at clear what the article I linked means when it says "This node is supported inside and outside the single-cycle Timed Loop if the target supports it."  Does the "it" at the end refer to SCTLs, the node, or the specific case of using the node inside a SCTL?  I know my target supports the first two because I've successfully used them already, it's the third case I'm trying to figure out.  If this it what that sentence is referring to, it seems a bit circular, and basically says "it's supported if it's supported".

Thanks for the help.

[Alex-C]

Hi,

I think the issue may lie with the NI 9222. Take a look at the following link:

NI 9222 (FPGA Interface)
http://zone.ni.com/reference/en-XX/help/370984T-01/criodevicehelp/crio-9222/

According to this, the NI 9222 does not support the single-cycle Timed Loop. I believe this is the issue that you are running in to.

Alex C.

National Instruments

Applications Engineer

[riplakish]

Hi Alex,

I see what you're referring to in the documentation.  So I guess if the module doesn't support SCTL then that includes not just read/write but all method/property nodes? Also when I look at the documentation for the other modules which support user controlled sampling it seems that none of them support SCTL, which makes the phrase in the original document a bit misleading (since it seemed to imply that some modules may support sample pulse generation in SCTL). Thanks for the help.

Regards

[Alex-C · Accepted solution]

Hi,

It is my understanding that if the module does not support the SCTL, then nothing associated with the module (be it read/write functions, IO Nodes, property nodes, etc.) can be used inside the SCTL. I looked into all the modules that support user controlled I/O, and did see that none of the modules support the SCTL.

It sounds like there is nothing inherent to the "Generate I/O Sample Pulse Function" that keeps it from working in the SCTL. It looks like the page for "Generate I/O Sample Pulse Function" was written this way in case any hardware in the future is created that does support both User Controlled I/O as well as the SCTL.

Alex C.
National Instruments
Applications Engineer