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FPGA Timing Violation -> How to find?

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Hi

I run into a timing violation problem during compiling my FPGA code. Even if I change the compile options to "balanced" or anything else the problem is still there.

My question is now, how can I find the function block in my code where the problem occurs? I use several SCTL's in my code.

 

thanks in advance

 

 

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Message 1 of 10
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Well your image shows that to meet timing requirements your code section needs a propagation delay of no more than ZERO seconds- obviously no amount of fiddling with compiler settings or code optimisation is going to meet this impossible target.

 

So question is, why is that the requirement? Have you set some kind of infinite loop rate?

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Message 2 of 10
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Hello

I think I found the problem according your reply. I forgot to use a while outside the SCT. Thanks for your answer.

 

 

best regards

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Message 3 of 10
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Somehow I still have the issue with a timing violation. Therefore I have following questions:

 

- Is the meaning of "Non-diagram component" the default value of my shift-registers (see vi)?

- If yes, why it can not be compiled in such way?

- How it can be solved?

 

 

 

 

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Message 4 of 10
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That non-diagram component is likely related to the cRIO variables you are using. Can you try changing your top-level clock to match your SCL clock and see if the error changes?

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the top level clock is per default 40MHz and can not be changed. Is it possible to use additional wait-loops or are there other ideas to solve this issue?

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...had a look to your FPGA vi but couldn't see a SCTL

The problem is probably caused by the use of the UserDefinedVariables. I suggest to replace them by controls or global variables. Unlike on other targets the use of global variables is suggested on FPGA's in terms of resource usage. I haven't used this type of variables on a chassis (FPGA) and as far as I understand the help, they work in scan mode which probably can't be combined within a FPGA vi. But LabVIEW throws no syntax error so I'm not sure...

 

Hope it helps

Christian

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Message 7 of 10
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I changed all SCTL with while-loops.

 

You mean I can use global variables to exchange data between the FPGA and a external Host-PC over the network? What is the best way

to exchange several data between FPGA and Host-PC in general?

 

thanks

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Message 8 of 10
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Solution
Accepted by topic author Norick_17

Use controls for the FPGA-Host communication as long as you have enough FPGA resources. It's recommended to use DMA FIFO communication between Host and FPGA.

Only the controls on the FPGA top level vi are accessible on the Host side.

 

Global variables are used to communicate with a FPGA scope only.

 

You use a sbRIO device so I think the FPGA shall communicate with the RT target (Host) ...

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Message 9 of 10
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I have a similar problem. My system is Flexrio with FPGA 7962R and IO module 6587. I am using external clock of 50MHz and basic connector clip. When I compile my code I to get error for Timing Violation. My program simply reads data from lvds read port, acquires 2 channels through indexing and saves data in DMA FIO (Target to Host) to be saved in TDMS format. 

If I run my code though internal clock, it works fine.

IF I run my code by replacing DMA fifo with an indicator and using external clock of 50MHZ, it works fine.

 

But IF I run my code using DMA fifo and external clock of 50 MHz i get timing violation error. on investigation, it calls DMA FIFO a non diagram components and the total delay exceeds with some ns. 

 

I want to know how should I remove this problem. I need to work with external clock and DMA fifo. 

Why is it calling it a non diagram component?

Secondly, How can we monitor/probe Timing delays of each function in FPGA VI? IS there some way of highlighting the function delay and then evaluating the total delay. 

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Message 10 of 10
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