FPGA Timed Loop - Set dt

[MrHappyAsthma]

Whenever I try to use a Timed Loop in LabVIEW FPGA, it doesn't give me the normal options to set the "dt" instance.  It works fine when I'm using timed loops on a Host VI, but not on the FPGA Target side.

This is what I see:

It shows the default clock as expected, but whenever I try to set another property, the only one available is the error:

Does anyone know how to set the "dt" timing parameter for a loop like this?  Thanks in advance! 🙂

[GerdW]

Hi Asthma,

on the FPGA that loop has a different name: SCTL aka Single Cycle Timed Loop!

Please read the LabVIEW help for that loop structure!

[MrHappyAsthma]

Where can the SCTL be found?  This is the only timed structure I can find anywhere on the pallette.  (If its not clear enough, I'm quite new to FPGA.  I also am in the process of transitioning to 2013 from 2009 so its a bit different 😛 )

[GerdW]

Hi Asthma,

the SCTL (on FPGA) looks like the TWL (on PC/Realtime), we are talking about the very same structure.

BUT: on the FPGA that loop behaves different than you are used to from PC/RT!

Read the help!

Go through FPGA basics found here (basics, paragraph 6)…

[MrHappyAsthma]

That video was quite informative.  Perhaps I have the wrong structure in mind then.  My goal is to repeat a loop, say 10000 times at exactly 2 kHz.  What would be the best approach to make this happen on the FPGA?

[GerdW · Accepted solution]

Hi Asthma,

use a FOR loop with a Wait(FPGA) in it…

Basics: Whenever you need to iterate for a given number of cycles you should use a FOR loop.

Basics: When your loop needs timing put a Wait in the loop…

[MrHappyAsthma]

Will do!  Thank you for the help and sorry for the confusion.  FPGA is quite a bit different than traditional LabVIEW on Windows.