FPGA Target

[fics]

Hi everyone!

I'm trying to resolve a problem by reading the FPGA Target with a Bitfile on the block diagram simulation. When I open the Open FPGA VI Reference I select the Bitfile and only the option Run the FPGA VI is crossed. Because I don't have the FPGA Module Software I'm using the Bitfile to know if a whole project works. I should mention that the FPGA Module hardware are there. I think I should set a resource name to the Open FPGA  VI  Reference. It appears errors that could be originated from the FPGA: Open FPGA VI Reference contains unwired or bad terminal. I'm not sure if the type of the Bitfile should be changed (boolean). I saw an example from NI for the Dynamic Host Interface and there is a block for the I/O RIO (nirio_resource_slv.ctl), which I tried to set on my project to see if that resolves the problem, but I don't find that block! It is a block for the FPGA Module Software? Or I'm looking wrong, and I need some driver? What could be the problem for the FPGA, that originated a bad terminal or is unwired?

A quick answer will be appreciated!

Thanks!

FICS

[Jacobson-ni]

Can you attach the VI that is giving you this error and tell us the error code that is being generated?

You are correct that if you point the Open FPGA VI Reference function to a bitfile you will need to specify an FPGA resource which will be an input to that function so that may resolve the error that you're talking about.

[fics]

Thanks, Jacobson, for your reply!

Your reply was filtered as spam...

Can you attach the VI that is giving you this error and tell us the error code that is being generated

Sadly I cannot attach the VI because it is big and is attached to others VI and the hardware part should also be installed; it isn't a simple project... I will attach pictures, where it seems the problem starts. Hopefully is still helpful to find a solution. There is more than 20 errors. 

You are correct that if you point the Open FPGA VI Reference function to a bitfile you will need to specify an FPGA resource which will be an input to that function so that may resolve the error that you're talking about.

Where I can find that block diagram? Or I need the FPGA Module Software for that? 

[Jacobson-ni]

---

@fics wrote:

You are correct that if you point the Open FPGA VI Reference function to a bitfile you will need to specify an FPGA resource which will be an input to that function so that may resolve the error that you're talking about.

Where I can find that block diagram? Or I need the FPGA Module Software for that? 

---

The FPGA host API is part of RIO driver. The issue with the first image is that you have a DMA FIFO called "FIFO1_......." that isn't defined in the Open FPGA VI reference in the right side of that image. Maybe it's just a different name, it could also be a FIFO you were referencing at one point and then deleted later on your FPGA.

[fics]

... At the moment I cannot know if that the problem was. There is a problem with the hardware. I'm going to post if the problem is resolved when I fixed the problem with the hardware part. 🙂