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FPGA - Slices over 100%

Is this ok?  It compiled ok but the slices are over 100%.  I don't have hardware yet to test so I thought I would ask if this is normal.

 

cRIO-9056

 

Compilation completed successfully.

Device Utilization
---------------------------
Total Slices: 104.3% (12312 out of 11800)
Slice Registers: 41.7% (39350 out of 94400)
Slice LUTs: 72.3% (34141 out of 47200)
Block RAMs: 6.7% (7 out of 105)
DSP48s: 32.8% (59 out of 180)

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If it says it was successful then it will probably work. I've had many at 100% that worked without issue. Utilization varies between compiles, so you can also try recompiling as the optimizer may do a better job and reduce the slices. You also have lots of resources still available, so there may be a way to rework your code to reduce slice utilization if it ends up not working.

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Do the compile logs give any hint?  I'm curious to see if there are shared resources that are being double counted so it's reporting over the max.

 

Interested to hear how deployment goes!

 

Regards,

Ben Johnson
ʕง•ᴥ•ʔง
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