07-09-2021 05:00 AM - edited 07-09-2021 05:03 AM
Hi all,
I would like to simulate serial port traffic. I have a library (IP) communicating on serial port (either connected to cRIO module NI 9870 or NI 9871). The library takes as inputs name of the port and FIFO for reading out commands, and outputs data read from the serial port to another FIFO.
Now if I would like to run this in simulator (so I will be able to unit test it), I don't see any option how to simulate serial port traffic. I understand how to simulate traffic on standard DIO using the Desktop Execution Node (DEN), but that doesn't allow to simulate serial ports. Neither I was able to simulate traffic using simulation VI specified in FPGA Target/Properties/Execution Mode.
I understand I can mitigate the problem by using FIFOs instead of serial port, and copy writes to serial port and reads from serial port. Is there a better option (as this will ask me to create a copy of library using FIFO instead of I/O reference).
The code in question is part of https://github.com/lsst-ts/Modbus_Processing_Unit
Thanks
07-09-2021 09:57 AM
Apparently, the option is to encapsulate read/write port functions in a class and create inherited class overloading port read/write with FIFO read/write. I was hoping for a more straight full approach.