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FPGA Set Output Data and Set Output Enable

According to Using Set Output Data and Set Output Enable - NI R Series Multifunction RIO Device Drivers Help - Na..., the Set Output data controls the data output for a digital line while the Output enable controls the direction. Logic high is output, low is input.

 

I have a FPGA I/O (DIO) that is normally reads a data from an external tristate device through a connector pin as an input DIO. When the external input is tri-stated, I can use the Set output data and .Set output enable to feed this same DIO as an output. The enable is a logic high for only the time the data is active. This works.

 

With the same DIO, I can use a FPGA DIO node to continuously read the DIO within the FPGA. From this, I see both the external data and the data I generated internally using the Set output data/Set output enable path. This works.

 

However, I had expected to see my internally generated data on the connector pin for the FPGA, but I only see the externally generated data.

 

If the output enable allows the DIO to be an output, then why don't I see the my generated output on the external connector pin?

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This issue is now resolved. The problem was that there was an external component that was driving the DIO low, creating contention. Once this contention was removed, the function works properly. I can now see my generated data, both internally and externally.

 

Using the Set Output data allows you to provide/change data to a given DIO, but it won't be seen until the enable is asserted. Using the Set Output enable, you control when the data is seen (both internally and externally at the same time). The same DIO can be read at any time.

 

The only requirement is if you are enabling an output on a DIO that is normally an input (input driven externally).For this case, you must ensure that the external network to the DIO is in high impedance when you enable your output for the DIO. So, yes, this is good for bi-direction communication.

 

If you use the DIO as an output only, the output enable could act as an independent pin gating function for the DIO (or a group of DIOs if you use the same enable for a port or a bus).

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