FPGA - Rate Limited Frequency Sine wave

[Allan_Mar]

I'm new to FPGA. What i'm trying to implement in a CRIO FPGA is a speed signal simulator.

Take a frequency, amplitude, and pos/neg rate limit from the host VI and output a corresponding speed signal.

The signal is 0-6000Hz, min 1hz step ( == .00015periods/tick) (conversion done in Host VI)

Looking to rate limit 0-6000Hz/s , min 100hz step(==slew rate step of 6.25E-14 periods/tick??) 48bit FXP?

Clock rate 40MHz

What i'm struggling with is how inefficent this appears to be. Because of the numbers i'm working with the fixed point's get very large. What's the best way to do this? Should I deal with larger numbers and then scale the input to the sine generator (in FPGA instead of host)?

I'm also going to end up with quite a few front panel objects? Whats the best way to handle that? (5 per speed signal and I have 5 speed signals)

[srm@viewpointusa.com]

this is pretty straight forward to implement.  if you look at the DDS examples for sine wave generation, you need to manipulate the increment value to change frequencies.  by rate limiting the change to the increment value, you have accomplished your goal.

this can be implemented in a loop for n generators.

however, if you are new to fpga, everything i have said may not make any sense.

[Allan_Mar]

I think it makes sense to me, the PNG in my post seems like it will work. What i'm struggling with is the specifics of how to implement it.

From the math in my first post, i need to use 48bit FXP numbers to manage the precision I need for these steps. This seems pretty inefficent, i'm trying to determine what the most efficent way is. Some kind of scaling? I'm pretty weak on fixed point math unfortunately.

[srm@viewpointusa.com]

yes, you are on the right track.

this implementation uses 64 bit fxp for rate limiting allowing you to run this at pretty much any speed.

there is still more optimization to be had in the sin wave generation for multiple channels but depending on your application, this may be enough.  the settings of each block count.

[Allan_Mar]

Thanks. That's a big help.

I guess what I wasnt sure of if thats very inefficent/poor practice. (all of the 64bit FXPs). Since I only need a limited range, but a fair bit of precision I was thinking about using smaller sizes and scaling the final frequency. I'm guessing that it's not really worth the hassle though.

Any hints regarding improving the generate sine for multiple signals (as you mentioned)?

Any performance improvements/suggestions for the front panel/data transfer (i'm going to have quite a few objects by the end of it with 4 per sine generator).

[srm@viewpointusa.com]

the 64 bit math (add and subtract) is not as bad as you might think.  this approach would be my preferred approach as it has the best balance of resource and performance.  i am not sure the scheme you are thinking of would be less resources and it would definitely not be as good a result.  is your application resource limited?  what else are you trying to pack into the FPGA?

here is a link to show some of the basics for DDS generation.  we used it as a starting point for an n-channel sin generator using only one lookup table.

http://zone.ni.com/devzone/cda/epd/p/id/6066 DDS Waveform Generation Reference Design for LabVIEW FPGA lvfpgaddsgen10rc1.zip

it doesn't make much difference if you use individual front panel controls or arrays or clusters.  it will generate the same amount of interface code.  it is more a preference for how you want to update the values from your host applicaiton.  all at once or individually.

[srm@viewpointusa.com]

this is the essence of a LUT based sin generator