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FPGA, RT and cRIO

Hi,

I have NI-9401 and NI- 9223 cards connected to the cRIO-9045 chassis.

My objective is read two analogue inputs at a rate of 1 MHz for 1 ms time period  (each channel collect 1000 data points in 1 mSec) using 9223 each time once 9401 detect a trigger signal.

I am trying to improve following RT and consist of FPGA target, RT target and FIFO. BAsically I am trying to understand how to collect 2000 data point in 1 ms (using two AI channes) and pass 2000 data points from FPGA to RT. I would appreciate if any suggestion/help

Thanks you

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Message 1 of 18
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I would probably use 2 DMA FIFOs, 1 for each channel.  You could possibly use a Single Cycle Timed Loop for your acquisition to save some fabric.  The loop should just read the channels and then write to the FIFOs.


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I can't tell what the datatype is for coming out of the analog reads, some sort of fixed point.  If those values are 32 bits or less, I would use a single DMA FIFO set for 64 bits, and pack the two values into a single 64 bit element and send that.  The RT code can then unpack the two values out of each element on the receiving end.

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Hi JayanthaS,

 

My objective is read two analogue inputs at a rate of 1 MHz

Then you should NOT put a 1µs wait into the FOR loop!

 

for 1 ms time period  (each channel collect 1000 data points in 1 mSec)

There also a loop is missing around the AI node to read 1000 samples…

 

each time once 9401 detect a trigger signal.

Here a case structure is missing!

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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Thanks for the suggestion!

Good idea I can implement 2 DMA FIFOs. However it did not let me use Timed loop with 9223 (gave a compile error) 

 

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I made the correction - could you take a look.

Data type is FXP

Many thanks

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Thanks for the help!

Here is latest code for FPGA and RT. My FPGA works well, however in RT application I get an error (-50400).

I would appreciate if any suggestion

regards

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Message 7 of 18
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Thanks for the help!

Here is latest code for FPGA and RT. My FPGA works well, however in RT application I get an error (-50400).

I would appreciate if any suggestion

regards

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Message 8 of 18
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I don't see the loop in your FPGA jpeg, so it only looks like you are writing 1 element to each FIFO.  Is there a loop?

 

Your RT jpeg shows you trying to read 1000 elements within 5 seconds.  Are you writing 1000 elements in the FPGA code fast enough?

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Hi Jayantha,

 

My objective is read two analogue inputs at a rate of 1 MHz for 1 ms time period  (each channel collect 1000 data points in 1 mSec) using 9223 each time once 9401 detect a trigger signal.

What I see in your "FPGA_c" image:

- you are waiting for a rising edge at DIO4, but the case structure after that IO node is acting on "Timed out". So your code in the case structure is called when there is a time out (aka NO rising edge)!?

- in the case structure is a FOR loop set to iterate just ONCE: this is pure Rube-Goldberg (aka non-sense)!

- in the loop you are reading just ONE sample from each AI: I thought your objective is to read 1000 samples?

- in the loop you are waiting for the next MILLIsecond multiple: I thought your objective is to read a sample each MICROsecond!?

 

Why do you think your "FPGA code runs well" when it does something completely different than your objective asks for?

 

In the RT code you should NOT try to run the FPGA code twice. Why do you split the FPGA reference wire (and the error wire) just before the FIFO.Start nodes? Why not use just one reference/error wire and call all nodes in serial? Why do you even try to close the very same FPGA reference twice???

Why is there a wait function in the RT main loop? The FIFO.Read nodes will do the timing!

 

There is so much wrong with your code.

Unfortunately you only attach images of the code, but not the code itself. If you intend to attach real code: ZIP the whole project including the lvproj file and all VIs and attach just the ZIP!

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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