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FPGA Loop delay not working

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How should that happen? 

 

The FPGA code runs independen of your host vi. 

And your latest vi has a path control, so that must be your host vi. 

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wiebe@CARYA wrote:

 In stead of running from a main VI, try running the VI directly on the FPGA. Then manually set the values from the FPGA VI while it's running. 

 

Put "i" on the from panel so you can watch it (either from the panel or from the host). That would be the clearest indication of the loop speed.


I was not even told, we could run directly without compiling the VI. Smiley Very Happy

Thanks. I am trying it now.

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@sivamit2002 wrote:

wiebe@CARYA wrote:

 In stead of running from a main VI, try running the VI directly on the FPGA. Then manually set the values from the FPGA VI while it's running. 

 

Put "i" on the from panel so you can watch it (either from the panel or from the host). That would be the clearest indication of the loop speed.


I was not even told, we could run directly without compiling the VI. Smiley Very Happy

Thanks. I am trying it now.


Sorry I think it still needs to be compiled. Smiley Indifferent

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@dkfire wrote:

How should that happen? 

 

The FPGA code runs independen of your host vi. 

And your latest vi has a path control, so that must be your host vi. 


Yes. It is.

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So how do you run your FPGA code from the host? 

How do you communicate with the FPGA?

 

And yes, you need to compile code that runs on FPGA, even if you click on the white run arrow.

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Message 15 of 27
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@dkfire wrote:

 

And yes, you need to compile code that runs on FPGA, even if you click on the white run arrow.


To be exact: you need to compile code that runs on FPGA once, even if you click on the white run arrow.

 

You don't need to compile it each time you click the run arrow. If it was changed, you need a recompile (even when all changes are just cosmetic)...

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This might help to understand. The channels have been configured for AOs

 

 

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I am a little unclear on the overall aims:

  1. Send commands to an FPGA, commands are contained in an array
  2. Have the FPGA operate on the commands with a certain delay between each operation
  3. When all the commands have been sent, stop the system

I do not see how the number of ticks that the FPGA has performed is calculated. So I do not see how the delay is implemented. The use of the while loop (instead of a single cycle timed loop; SCTL) on the FPGA means that the contents do not necessarily operate in a single clock cycle. You are assuming that each cycle of the while loop takes a tick of your 40 MHz clock, using a while loop means that this is not the case (due to dataflow, ask if you want to know more!). To be clear, the operation while take a determined and constant period, you just don't know its length a priori when you use a while loop.

 

Here are some key steps to the FPGA program I think you want:

  1. Initialise a tickCount to 0, initialise cmdCount to 0
  2. If Run=true, increment the tickCount, set progComplete to false
  3. Perform the required action, send FXPs to AO etc. etc....
  4. Check if tickCount is equal to the tickLimit, if so, reset the tickLimit, increment cmdCount
  5. Check is cmdCount is equal to cmdLimit, if so, set progComplete to true

Step one is represented by the inputs into a shift register on the SCTL. Steps 2-5 all occur within a single cycle of a SCTL. Run is a command sent from the host which sets off the process. tickLimit and cmdLimit are also commands sent from the host.

 

You can include some other indicators to show the state; tickCount, cmdCount and progComplete would be interesting, for instance.

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@MaxJoseph wrote:

I am a little unclear on the overall aims:

  1. Send commands to an FPGA, commands are contained in an array
  2. Have the FPGA operate on the commands with a certain delay between each operation
  3. When all the commands have been sent, stop the system

 


Hi MaxJoseph,

1. I am trying to control the speed of a motor by sending AO output. I have a profile that adjusts the speed(voltage out) over a period of 65 seconds i.e with the sample rate 1000, I would have 65000 samples in an array, with different amplitude values, to vary the speed of the motor depending on the requirement.

 

2. Sample rate may not always be 1000 Hz. It may be 20- 1000. but the time axis 65 seconds(executing time) wont change. If my sample rate is 100, no. of samples is 6500 but I still need to distribute these sample for 65 seconds .So i would introduce a delay of 10ms(this is where my code stuck. The loop delay change is not working Smiley Sad) so I will still execute the samples for 65 seconds.

3. This is the requirement of the test. I don't need to operate my motor after the test.

Hope you underatand.

 

I will try whatever you told me. I am new to this FPGA world. So.it might take a little while.

 

Thanks.

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Message 19 of 27
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@MaxJoseph wrote:

 

I do not see how the number of ticks that the FPGA has performed is calculated. So I do not see how the delay is implemented. The use of the while loop (instead of a single cycle timed loop; SCTL) on the FPGA means that the contents do not necessarily operate in a single clock cycle. You are assuming that each cycle of the while loop takes a tick of your 40 MHz clock, using a while loop means that this is not the case (due to dataflow, ask if you want to know more!). To be clear, the operation while take a determined and constant period, you just don't know its length a priori when you use a while loop.

 

Here are some key steps to the FPGA program I think you want:

  1. Initialise a tickCount to 0, initialise cmdCount to 0
  2. If Run=true, increment the tickCount, set progComplete to false
  3. Perform the required action, send FXPs to AO etc. etc....
  4. Check if tickCount is equal to the tickLimit, if so, reset the tickLimit, increment cmdCount
  5. Check is cmdCount is equal to cmdLimit, if so, set progComplete to true

Step one is represented by the inputs into a shift register on the SCTL. Steps 2-5 all occur within a single cycle of a SCTL. Run is a command sent from the host which sets off the process. tickLimit and cmdLimit are also commands sent from the host.

 

You can include some other indicators to show the state; tickCount, cmdCount and progComplete would be interesting, for instance.


I can't use the SCTL - I can't compile without error.

 

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