Showing results for 
Search instead for 
Did you mean: 

FPGA Indicators

Go to solution

Hello all


I know in order to optimize the speed the FPGA can run, I need to limit the amount of indicators on the FPGA front panel and use DMA FIFOs where appropriate. Where I'm confused is I am unsure at what data size it is more efficient to use a DMA FIFO. I have 13 indicators in my FPGA code, and am not sure what data transfer mechanism to use. Thanks.

0 Kudos
Message 1 of 2
Accepted by topic author Schrodinger1933

There are two main methods to transfer data from your FPGA to RT target - front panel controls/indicators and DMA FIFOs. DMA FIFOs are going to be the fastest method if you are transferring large amounts of data between FPGA and RT, while front panel control/indicators will be dependent on the speed and availability of the host processor and are better for small/infrequent data transfers.


For more information on these two methods, I would consult the cRIO Developer's Guide (starting on page 89).


Additionally, here is a help document for optimizing FPGA VI speed.

Message 2 of 2