FPGA Implemenation of Single Pole Double Throw

[SmplLbV123]

I have a PXI-7833R FPGA board. I have an input that is connected to ground at Connector0/DIO0. How do I implement with LabVIEW FPGA where I can cyclically in a loop switch my input (Connector0/DIO) to Connector0/DIO1, hold it there for 1 second, then switch my input to Connector0/DIO2, hold it there for 1 second, then back to Connector0/DIO1?

The attachement is my fist crack at it. Does it look right?  My concern is that after switching from Connector0/DIO1 to Connector0/DIO2 my external circuitry that is connected to Connector0/DIO1 will not be seeing an open circuit, like I would with a traditional single pole double throw switch.

Thanks!

[Dragis]

I had to dig around a bit, but I believe this is what happens with digital IO.

1. When the device powers on, all digital IO is put into tristate (read) mode.

2. When you write a value to digital IO, it implicitly changes the output mode to drive the value you wrote.

3. Reading from the digital IO will NOT tristate the pin again. To do that, you need to use the "Set Output Enable" method on the that IO pin.

As to your design, you need to do one extra step which is to tristate the appropriate pin between each transition of the system.

[SmplLbV123]

So...basically, setting the "Set Output Enable" to FALSE would similarly setting a Digital Ouput line to a high impedance? (VHDL code would be setting it to Z)