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FPGA IO Node and Loop Timing Question

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I am having a lot of trouble compiling a very simple FPGA VI for a DAQ system on my cRIO (cRIO 9075, using a single 9205 module, labview 2012 dev suite, xlinx13).

 

The error occurs at the very end of the compilation if and only if I use an FPGA I/O Node block.  This image shows my very simple VI that fails a compile:

Fail - Block.PNG

 

When I compile it, I get this error at the very end:

 

Fail - Summary.png

 

 

 And here are the details of the error:

 

Fail - Details.png

 

It is also worth noting that the 'Timing Summary' says that I need an 80MHz clock, when the onboard clock is only 40MHz.

 

For comparison, when I remove the FPGA I/O Node and replace it with a constant, the compilation succeeds:

 

Pass - Block.PNG

 

Also, the need for an 80MHz clock disappears from the timing report.

 

 

Is this an issue with the way loops work in FPGAs?  I have read a lot about "single cycle timed loops" that guarantee one execution per clock cycle.  I do not need this sort of acquisition rate, and I assume that the loop structure I created is not bound to a single cycle because of the metronome block I inserted.  Am I assuming correctly?  Are there even any loop structures for FPGAs that are not bound to a single clock cycle?

 

I also wonder if this error is does not have to do with my code, but is instead an error internal to the NI compilation software, particularly the 'niFpgaTimingViolation.py' script mentioned in the detailed error summary.  I did have labview 2011 and xlinx 12 installed on this computer before, but uninstalled them before upgrading.  This is my first project in 2012.

 

I appreciate any feedback from the NI community.  Let me know if my question needs any further clarification.

 

-Andrew

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Andrew,

 

Just to clarify, you are using LabVIEW FPGA 2012. What version of the compilation tools do you have installed?

 

I built essentially a copy of your VI and had no problems compiling. I used a 1000 tick loop timer and a target to host DMA FIFO on the same hardware described in your post.

 

Capture.JPG

 

I'd like to take a look at your project and VI if you wouldn't mind posting it here. I want to try and compile your VI from my machine and look at the xilinx logs should it fail.

Nick C | Software Project Manager - LabVIEW Real-Time | National Instruments
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Solution
Accepted by topic author aburks

I solved the problem.

 

In case anyone searches for this later (Error 61499 niFpgaTimingViolationMain.py ConstraintDict is not defined).

 

I did a complete uninstall and reinstall of my entire LV 2012 dev suite.  Then the same VI that used to fail compile started to pass compile.  Apparently I had a corrupt file somewhere.

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