FPGA I/O Limitation? Bug?

[KieranW]

Good day,

Is there a limit on having more than one FPGA I/O node within a case structure on the FPGA? I have a program that executes fine when only one case has a I/O node but when two or more nodes exist within the same structure the AO card Im using gives a 0 no matter what is wired to it. Is this a bug or a software limitation?

I've been unable to find documentation on this so if someone could assist me that would be really appreciated.

[KieranW]

Is anyone able to assist with this? This is a major sticking point for me and is quite a serious issue if it's not intentional.

[kartiknattar]

I guess you can do that. Can you upload your fpga project?

[paul.r]

I don't think anyone is going to be able to give you meaningful help without more details. What's your hardware setup? Can you share your code? If not, can you recreate the problem with a really simple example? 

[Terry_ALE]

I do not believe there is a limitation.  You can have more than one I/O node in a case structure.

For an Analog Output application I would hold the last values in a shift register and always write to the values of the channels you are using.

[KieranW]

Thank you for the reply.

I've attached a simplified example code that has the same issue.

The Hardware I am using is an cRIO-9030 with an NI-9262 Analogue Out card.

The "Data Check" Indicator shows me that when Run is pushed, the data being wired to the IO node is correct - from 0 to 5V in steps according to the number of samples. However what I can see on an attached oscilloscope is just 0V from the card. I know the card works because if I change the value of the constant in the "standby" state, I see that being correctly output by the card. I can also see the oscilloscope is working using external sources.

[paul.r]

Hmm.. So to confirm, if you take that example, and change the IO nodes from being Channel 1 and Channel 2 to just being Channel 1 or Channel 2 you see the correct output? 

[KieranW]

Apologies, I don't think I explained very well.

I only see the correct output when I remove the IO node from the standby case. Having the multiple channels has no affect.

What happens is that when you push run (regardless of the values wired to IO node in either case) the card outputs a 0 where it should be outputting other values, then when it is has finished it goes back to the value wired to the standby case.

That is to say, if I changed the value wired to the IO node in the standby case to 3V, I would see 3V on my oscilloscope. When I then push run, it changes to a 0 for however many samples there is, then back to 3V when the run case is done.

[hacknode]

hello，may i ask that the issue with 9262 in FPGA  you mentioned had be sovled?

[KieranW]

Hello.

Actually no, I ended up just avoiding the use of two I/O nodes because after a lot of searching and troubleshooting, I could not find an answer.